Stmicroelectronics Pvt. Ltd.

Srijib Narayan

Kaushik Saha

The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first 'logP' stages for an implementation using 'P' processing elements, comprising computing each butterfly of the first &#x201c;logP&#x201d; stages on either a single processor or each of the &#x201c;P&#x201d; processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the &#x201c;P&#x201d; processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor. The embodiments of the invention also provide a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first &#x201c;logP&#x201d; stages for an implementation using &#x201c;P&#x201d; processing elements.

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West Bengal, India

Srijib Narayan