Stmicroelectronics International N.v.

Aura Semiconductor Pvt. Ltd

St-Ericsson Sa

Sriharsha Vasadi

Ankit Seedher

Shyam Somayajula

Srinath Sridharan

Raja Prabhu J

Augusto Marques

A phase frequency detector (PFD) includes a first circuit portion and a second circuit portion. The first circuit portion receives a reference signal and activates a first error signal if the phase of the reference frequency leads the phase of a feedback signal. The second circuit portion receives the reference and activates a second error signal if the phase of the reference frequency lags the phase of the feedback signal. The first circuit portion is powered by a first power supply, and the second circuit portion is powered by a second power supply. A PLL implemented using the PFD generates a frequency output with minimized jitter.

Reducing errors due to non-linearities caused by a phase frequency detector of a phase locked loop

Systems and methods provide for a power management unit and its operation. The power management unit includes: a step-down power converter configured to receive a first voltage and output a second voltage, wherein the second voltage is less than the first voltage and at least one step-up power converter configured to receive the second voltage and output a third voltage, wherein the third voltage is greater than the second voltage. It also includes an inductive element connected to the step-down power converter and the at least one step-up power converter and configured to store energy and selectively release the stored energy, wherein the inductive element is time shared by both the step-down power converter and the at least one step-up power converter; and a finite state machine configured to control the time sharing of the inductive element.

Power management unit systems and methods

Growing community of inventors

Bengaluru, India

Sriharsha Vasadi