Qualcomm Incorporated

Sriharsha Chakka

Navdeep Mer

Sharon Graif

Christopher Kong Yee Chun

Naveen Kumar Narala

John Milford Fletcher

Kishalay Haldar

Chris Rosolowski

Sreenivasan Jouly Jothiram

Viney Kumar

Jai Babu Mahankud

Sai Ganapathy Srinivasan

Various embodiments include methods for implementing command transactions on a two-wire bus system of a computing device, and devices for implementing the methods. Embodiments may include receiving, by a two-wire interface of a host device, an abort signal via a two-wire bus, and transmitting, by the two-wire interface of the host device, an end signal via the two-wire bus in response to receiving the abort signal. Embodiments may further include transmitting, by a two-wire interface of a bus owner device, commands via the two-wire bus prior to receiving the end signal, receiving, by the two-wire interface of the bus owner device, the end signal via the two-wire bus; and terminating, by the two-wire interface of the bus owner device, transmitting commands in response to receiving the end signal. Some embodiments may include transmitting the commands following an instance of bus arbitration and prior to a subsequent instance of bus arbitration.

Multi-command transactions

Systems, methods, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes receiving a write command from the serial bus in a datagram, writing a data byte received in a first data frame of the datagram to a register address identified by the datagram, and using a second data frame of the datagram to provide feedback regarding the datagram. Feedback may be provided by driving a data line of the serial bus to provide a negative acknowledgement during the second data frame when a transmission error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgement of the datagram.

Providing acknowledgements for system power management interface

Systems and methods for bus clock line handover are disclosed. In one aspect, a clock line in a bus is driven continuously during bus handover without having contentious or contradictory drive signals being provided. After arbitration, an original bus master will drive the clock line to a predetermined value until detecting a state change on a data line. An incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line.

Bus clock line handover systems and methods

The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

Hang correction in a power management interface bus

The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

Growing community of inventors

Bengaluru, India

Sriharsha Chakka