Intel Corporation

Srihari Makineni

Ravishankar Iyer

Donald K Newell

Li Zhao

Rameshkumar G Illikkal

Jaideep Moses

Zhen Fang

Andrew J Herdrich

Xiaowei Jiang

Ravi Iyer

Sujoy Sen

Ramesh Kumar Illikkal

Sadagopan Srinivasan

Stephen T Palermo

Lokpraveen B Mosur

Dave B Minturn

Neelam Chandwani

Shubha Bommalingaiahnapallya

Udayan Mukherjee

Shrikant M Shah

Adwait Purandare

Rany T Elsayed

Dmitri Yurievich Pavlov

Ramesh G Illikkal

Simon C Steely, Jr

Christian Maciocco

Shih-Lien L Lu

Ankush Varma

John Joseph Browne

Chris MacNamara

Vasudevan Srinivasan

William C Hasenplaugh

Antonio Gonzalez

Fernando Latorre

Manav Mishra

Tomasz Kantecki

Aamer Jaleel

Leena K Puthiyedath

David B Minturn

Pedro Lopez

Nikhil Gupta

Dorit Shapira

Jaume Abella

Josep M Codina

Rajesh Gadiyar

David Hunt

Uzair Qureshi

Pinkesh J Shah

Linda S Cline

Jose-Alejandro Pineiro

Enric Gibert

Don Newell

Hongliang Gao

Sadogopan Srinivasan

Anatoly Burakov

Bryan T Butters

Rany ElSayed

An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

Systems, methods, and apparatus for workload optimized central processing units (CPUS)

Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

Frequency scaling for per-core accelerator assignments

Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

Platform slicing of central processing unit (CPU) resources

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Power efficient processor architecture

In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

Packet coalescing

An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

Interrupt return instruction with embedded interrupt service functionality

In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

Embedded branch prediction unit

An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.

Efficient locking of memory pages

Growing community of inventors

Portland, OR, United States of America

Srihari Makineni