Intel Corporation

Sridharan Ranganathan

David J Harriman

Satheesh Chellappan

Mahesh U Wagh

Karthi R Vadivelu

Anoop Mukker

Zeeshan Sarwar

Shalini Sharma

Vinu K Elias

Paul S Durley

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Configuring a remote M-PHY

A close proximity wireless connection is initiated between a first device and a second device, and a channel configuration module sends first data over the wireless connection to advertise one or more supported channel configurations of the first device to the second device, and receives second data over the wireless connection. The second data is to advertise one or more supported channel configurations of the second device to the first device. A particular one of a plurality of modes of the first device is determined to be used in communications with the second device over the close proximity wireless connection based on the first and second data.

Close proximity transport configuration

Techniques and mechanisms to provide common interface logic for multiple protocol engines to access physical layer circuitry at different times. In an embodiment, a state machine of an interface device is to participate in exchanges with physical layer resources on behalf of any of various protocol engines coupled to the interface device via different respective interfaces. Based on state transitions by the state machine, circuitry corresponding to a particular one of such interfaces may selectively send a clock signal for operation of a port controller attempting to access the physical layer circuitry. In some embodiments, multiple interface devices are configured to provide an hierarchical interface architecture for more than two port controllers that variously support at least two protocols.

Apparatus, system and method for sharing physical layer logic across multiple protocols

Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal Serial Bus (USB) physical subsystem and system firmware, wherein the system firmware conveys USB related events to the SOC. The system is configured to include a power management apparatus, where the power management apparatus includes USB wake functionality and USB On-the-Go (OTG) functionality.

Block partition to minimize power leakage

An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.

Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Inter-chip communications with link layer interface and protocol adaptor

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Providing a load/store communication protocol with a low power physical unit

Superspeed inter-chip interface

Techniques are provided for image decompression. Compressed pixels are pipelined through various decompression processes. As contexts for some pixels are resolved, the resolved contexts are fed back into selective portions of the decompression processes in order to resolve contexts for other pixels currently being processed.

Techniques for image decompression

In one embodiment, the present invention includes an apparatus that has a plurality of buffers to store data resulting from operations of a processor pipeline, a pointer storage to store pointers, where each of the pointers is to point to one of the buffers, and one or more resources coupled to the buffers to receive the data stored in the buffers. Other embodiments are described and claimed.

High performance architecture for a writeback stage

A technique to perform error distribution in a graphics system. More particularly, embodiments of the invention include at least one technique to distribute the error resulting from converting computer generated graphics pixels from one pixel depth to another.

Growing community of inventors

San Ramon, CA, United States of America

Sridharan Ranganathan