Sandisk Technologies Inc.

Sridhar Yadala

Sravanti Addepalli

Gooty Sukumar Reddy

Ravindra Arjun Madpur

Subodh Taigor

Sivakumar Grandhi

Rangarao Samineni

Potnuru Venkata Pradeep Kumar

Nittala Venkata Satya Somanadh Kumar

Raul-Adrian Cernea

Kirubakaran Periyannan

Loc Tu

Saurabh Kumar Singh

Saurabh Kumar Verma

Anirudh Amarnath

Dat Tran

Hitoshi Miwa

Amandeep Kaur

Jayanth Mysore Thimmaiah

Hemant Shukla

Deepak Kumar Meher

Prajit Nandi

Pradeep Anantula

Venkata Nittala

Sowjanya Sunkavelli

VSNKChaitanya G

Anupam G N Choudhary

Addagalla Aswani Krishna Lakshminarayana

Kishan Santoki

Sowjanya Tungala

Sini Balakrishnan

Aswani Krishna Lakshminarayana Addagalla

Vivek Venkata Kalluru

Sriganesh Chandrasekaran

A method for trimming analog temperature sensors. First, raise a temperature of a temperature sensor to a highest temperature of a qualification temperature range. Then, trim the temperature sensor such that a high temperature code generated by the temperature sensor represents an actual temperature reported by the temperature sensor at the highest temperature. Next, lower the temperature of the temperature sensor to a lowest temperature of the qualification temperature range. Determine a slope error between the high temperature code and a low temperature code generated by the temperature sensor at the lowest temperature. Finally, determine a correction function that compensates for the slope error of measured temperature codes generated by the temperature sensor for temperatures across the qualification temperature range.

Apparatus, system, and method for trimming analog temperature sensors

A temperature sensing circuit of a data storage system includes a temperature sensor, a digital-to-analog circuit, and a reference generation and trimming circuit configured to generate a common mode voltage (VCM), a positive reference voltage (VREFP), and a negative reference voltage (VREFN) using a single band gap reference signal. The trimming circuit is configured to trim the VCM, VREFP, and VREFN by adjusting a VC trim signal to increase the VCM until a VCM error is below a threshold; adjusting a high temperature trim signal to increase the VREFP and decrease the VREFN until a digital temperature signal associated with the digital-to-analog circuit attains a predetermined accuracy level for a first temperature; and adjusting a low temperature trim signal to increase the VREFP, VCM, and VREFN until the digital temperature signal attains a predetermined accuracy level for a second temperature.

Two way single VREF trim for fully differential CDAC for accurate temperature sensing

An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage block of a non-volatile memory array by way of the switching circuit. A memory current is generated within the set of word lines. A leakage code is determined for the set of word lines representing leakage current from the word lines in response to the memory current. The leakage code is compared with the reference code. If the leakage code exceeds the reference code, the storage block is deemed unusable.

Non-volatile memory array leakage detection

A sense amplifier for a memory circuit is presented that can reduce sensing times by introduction of a local reference generator. The sense amplifier includes two capacitors that are pre-charged prior to a sensing operation. A first of the capacitors is connected so that it can discharge through a selected memory cell at a rate dependent on the conductivity of the selected memory cell. After a sensing interval in which the first capacitor can discharge through the selected memory cell, the voltage level on the first capacitor is compared with the voltage level on the second capacitor to determine the result of the sensing operation.

Sense amplifier architecture providing improved memory performance

A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.

Systems and methods for capacity management of a memory system

A bandgap reference generation circuit in an integrated circuit (IC) and method for generating a bandgap reference voltage are disclosed. The bandgap reference generation circuit includes a first proportional to absolute temperature (PTAT) current generation section for generating a PTAT current component, a current circuit configured to generate a trimmed PTAT current component substantially invariant of sheet resistance of at least one resistor in the current circuit, and a complementary to absolute temperature (CTAT) current generation section including a diode on which the trimmed PTAT current component is fed to generate a CTAT current component. A combination of the PTAT and CTAT current components generate the bandgap reference voltage.

Bandgap reference generation circuit

Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.

Self testing circuit for power optimization

A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.

Duty cycle and skew correction for output signals generated in source synchronous systems

The peak voltage at which a voltage-setting transistor is driven is reduced while the body effect of the transistor is also compensated. The voltage-setting transistor is driven at an initial level and then coupled higher by a capacitor which is connected to the control gate of the voltage-setting transistor. The amount of coupling can vary as a function of an assigned data state of a memory cell connected to the transistor by a source line and/or bit line. The capacitor may have a body which is common to a set of memory cells. The voltage can be set prior to applying a program voltage to the control gate of a memory cell to control a programming speed of the memory cell based on its assigned data state. The voltage can also be set in connection with a sensing operation.

Method and apparatus for coupling up a voltage-setting transistor for a control line in a programming operation

Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a controller and then is ended when the output voltage of the voltage regulator is within a first voltage of the desired regulation voltage or has overshot the desired regulation voltage by a second voltage (e.g., has overshot the desired regulation voltage by 150 mV).

Fast settling low dropout voltage regulator

A charge pump is connected to receive a supply voltage and a clock signal and generate an output voltage. The charge pump is connected to the supply voltage through a transistor whose gate voltage is set by a regulation voltage determined by feedback from the output voltage. The current supplied to the charge pump through this transistor is mirrored in a section that generates the clock signal, where the mirrored current is used by a current controller oscillator. This allows the pump's clock frequency to linearly track the load current, improving the pump's efficiency.

Dynamic clock period modulation scheme for variable charge pump load currents

Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be based on a reference voltage and a target calibration resistance.

Temperature independent reference current generation for calibration

A charge pump design suitable for generating high voltages employs multiple low voltage capacitors and low voltage transfer switches, with a limited number of high voltage devices. This is designed such that during a first clock phase, capacitors are each connected between an input voltage and ground and, during a second clock phase all the capacitors are connected in series to generate the required voltage. Both the switches (PMOS) and as well the capacitors are realized as low voltage devices. The ability to use low voltage devices can significantly reduce the area and also a reduction in current consumption relative to the usual high voltage charge pumps which uses high voltage devices.

High voltage generation using low voltage devices

Techniques for trimming an on chip ZQ calibration resistor are disclosed. The on chip ZQ calibration resistor alleviates the need for an external ZQ calibration resistor. The on chip ZQ calibration resistor allows for a faster ZQ calibration. The trimming of on chip ZQ calibration resistor may be used to account for process variation. A correction mechanism may be used to account for temperature variation. Some of the circuitry that is used for ZQ calibration is also used for trimming the on-chip calibration resistor. This circuitry may include operational amplifiers, current mirrors, transistors, etc. The dual use of the circuitry can eliminate offset errors in an operational amplifier. The dual use can eliminate current mirror mismatch. Therefore, the trimming accuracy may be improved. The dual use also reduces the amount of circuitry that is needed for trimming the on chip ZQ calibration resistor. Thus, transistor count and chip size is reduced.

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Bengaluru, India

Sridhar Yadala