Intel Corporation

Sridhar Tirumalai

Bryan K Casper

Aaron K Martin

Ganesh Balamurugan

Frank Patrick O'Mahony

Mozhgan Mansuri

Navneet Dour

Roger K Cheng

Ajay Balankutty

Kuan Zhou

Krishnamurthy Venkataramana

Alex Thomas

Quoc Nguyen

Hari Venkatramani

Andrew M Volk

Amir Bashir

Jing Li

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)

A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

Fast lock scheme for phase locked loops and delay locked loops

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Chandler, AZ, United States of America

Sridhar Tirumalai