Synopsys, Inc.

Trupik, Inc.

Sridhar Tirumala

Qiang Chen

Vikranth Katpally Reddy

Aravind Inumpudi

Qian-Ying Tang

David Joseph Harmon

Akash Jain

Shivani Pulimamidi

Exemplary embodiments described herein relate to systems and methods for generating an image comprising a three-dimensional ('3D') model or replica of a subject. Such images may include the face of a human subject as well as views of the subject from various angles.

Systems and methods for image generation and modeling of complex three-dimensional objects

Embodiments of the present disclosure can be used to generate an image replica of a person wearing various outfits to help the person visualize how clothes and accessories will look without actually having to try them on. Images can be generated from various angles to provide the person an experience as close as possible to actually wearing the clothes, accessories and looking at themselves in the mirror. Among other things, embodiments of the present disclosure can help remove much of the current uncertainty involved in buying clothing and accessories online.

Image morphing processing using confidence levels based on captured images

An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Modeling of cell delay change for electronic design automation

A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results.

Integrated circuit optimization modeling technology

An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for adjustment of the circuit parameter. A shape modification calibrated to achieve the desired adjustment is selected from the library. The shape modification is applied to the identified cell in the layout file to produce a modified layout file. The modified layout file can be used for tape out, and subsequently for manufacturing of an improved integrated circuit.

Optical proximity correction aware integrated circuit design optimization

A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values.

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Saratoga, CA, United States of America

Sridhar Tirumala