Mentor Graphics Corporation

Siemens Industry Software Gmbh

Sridhar Srinivasan

Mark E Hofmann

Patrick D Gibson

Padmaja Susarla

Yi-Ting Lee

Fedor G Pikus

Valeriy K Sukharev

William Matthew Hogan

Sandeep Koranne

Sherif Hany Riad Mohammed Mousa

Ziyang Lu

Armen Asatryan

Grigor Geoletsyan

Gregory P Hackney

Hung-Hsu Feng

Alex Thompson

Lei Ling

Chung Lee

A circuit design in a hierarchical description is analyzed. The analysis comprises identifying electrical properties of circuit blocks in the circuit design. Circuit components of the circuit design are associated with geometric elements of a layout design. Then instances of each of the circuit blocks are classified into groups of instances based on the electrical properties. Rule checking is performed on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.

Automatic identification of hierarchical cells based on selected properties for layout verification

Systems and methods for efficient bi-directional property-based path tracing. The method includes reading a data structure corresponding to a circuit. The method also includes iteratively performing property accounting of properties as voltages propagate across devices in the circuit. The method also includes traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties (e.g. shortest distance) remain unchanged between subsequent iterations of the traversing. The method also includes traversing the data structure for propagated user-specified and computed property violations. The method also includes cataloging and reporting these violations in human-readable form.

Efficient bi-directional property-based path tracing

Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.

Automatic moving of probe locations for parasitic extraction

A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.

Logic-driven layout verification

Aspects of the disclosed technology relate to techniques of parasitic extraction using compact representation of process calibration data. Geometric information of a layout feature in the layout design comprising geometric parameters is extracted. Parasitic values associated with the layout feature are then computed based on the geometric information and one or more executable files selected in a plurality of executable files which are a compact representation of process calibration data.

Parasitic extraction based on compact representation of process calibration data

Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information.

Resistor network reduction for full-chip simulation of current density

Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. Voltage values are propagated across components of a circuit design through global iterations until voltage values on nets of the circuit design are not changed from one global iteration to a next global iteration or one preset condition is met. At least one of the global iterations comprises local iterations for a subcircuit of the circuit design. The local iterations suspend when voltage values on nets of the subcircuit are not changed from one local iteration to a next local iteration or one preset condition is met. The propagated voltage values are then analyzed to detect problems in the circuit design.

Acceleration of voltage propagation based on local iteration

Aspects of the disclosed technology relate to techniques of scoped simulation-based ESD verification. ESD (electrostatic discharge) protection devices and I/O (input/output) circuitry are identified in a circuit design. Static simulation is performed on the I/O circuitry to determine voltage and current information for devices on current paths in the I/O circuitry based on point-to-point resistance values. Transient simulation is then performed on one or more of the ESD protection devices in the devices based on the voltage and current information and detailed parasitic information. The point-to-point resistance values and the detailed parasitic information are extracted based on a layout design for the circuit design and cross-reference information between circuit component identifiers and layout features. Results of the transient simulation are analyzed to identify ESD protection problems.

Scoped simulation for electrostatic discharge protection verification

Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.

Reliability verification based on combining voltage propagation with simulation

Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.

Connectivity-aware layout data reduction for design verification

This application discloses a voltage analysis tool to perform a static power aware analysis on a circuit design without having to simulate the circuit design. The voltage analysis tool can determine a set of components in the circuit design corresponds to a design pattern representing a voltage-transition device, and set an output voltage for the set of components based, at least in part, on characteristics of the voltage-transition device. The voltage analysis tool can propagate the output voltage to other portions of the circuit design, and determine whether the portions of the circuit design receiving the output voltage have a rule violation.

Programmable pattern aware voltage analysis

Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.

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Tualatin, OR, United States of America

Sridhar Srinivasan