Intel Corporation

Sridhar Samudrala

Robert Valentine

Bret L Toll

Jeffrey G Wiedemeier

Elmoustapha Ould-Ahmed-Vall

Edward Thomas Grochowski

Milind Baburao Girkar

Robert Dale Cavin

Andrew Thomas Forsyth

Dennis Ryan Bradford

Jonathan Cannon Hall

Suleyman Sair

Grigorios Magklis

Seth Abraham

Charles R Yount

Jesus Corbal San Adrian

Marc Lupon

James Charles Abel

Lisa K Wu

Santiago Galan Duran

Roger Espasa Sans

Mark Jay Charney

Roger A Golliver

David Roger Ditzel

Jeff Wiedemeier

Raul Martinez

Enric Gibert Codina

Kyriakos A Stavrou

Jesus Corbal

Eric W Mahurin

Linden Cornett

Anjali Singhai Jain

Daniel Daly

Kiran A Patil

Namrata Limaye

Mark Charney

Phani Burra

Brett Creeley

Venkata Suresh Kumar Paruchuri

Robert C Valentine

Methods and apparatus for extending OpenvSwitch (OVS) megaflow offloads to hardware to address hardware pipeline limitations. Under a method implemented on a compute platform including a Network Interface Controller (NIC) having one or more ports and running software including OVS software and a Linux operating system having a kernel including a TC-flower module and a NIC driver a new megaflow is created with a mask in the OVS software employing a subset of microflow fields for a packet. The microflow fields and the megaflow mask is sent to the NIC driver. A new megaflow is implemented in the NIC driver employing a subset of the microflow fields and the NIC driver creates a new hardware flow on the NIC employing a packet match scheme using all the microflow fields. The NIC also programs a NIC hardware pipeline with the new hardware flow using a match scheme that may depend on the available hardware resources, such as the size of a TCAM.

Extension of openvswitch megaflow offloads to hardware to address hardware pipeline limitations

Examples described herein relate to one or more processors, when operational, to execute instructions stored in memory device, to cause performance of: execute a driver that is to: negotiate capabilities of hardware with a control plane for a virtualized execution environment and limit capabilities of the hardware available to the virtualized execution environment based on a service level agreement (SLA) associated with the virtualized execution environment. In some examples, the driver is to advertise hardware capabilities requested by the virtualized execution environment. In some examples, the control plane is to set capabilities of a hardware available to the virtualized execution environment based on the SLA.

Technologies that provide policy enforcement for resource access

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.

Instruction and logic to provide vector blend and permute functionality

Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

Double rounded combined floating-point multiply and add

An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.

Combined floating point multiplier adder with intermediate rounding logic

A mechanism is described for facilitating dynamic and efficient fusion of computing instructions according to one embodiment. A method of embodiments, as described herein, includes monitoring a software program for a program region having fusion candidate instructions for a fusion operation at a computing system; evaluating whether the macro operation of the candidate instructions is valuable to the software program; and performing the fusion operation if it is evaluated to be valuable.

Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs

A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.

Vector logical reduction operation implemented using swizzling on a semiconductor chip

A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.

Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation

Growing community of inventors

Austin, TX, United States of America

Sridhar Samudrala