Western Digital Technologies, Inc.

Sridhar Prudvi Raj Gunda

Lalit Mohan Soni

Yehuda Hahn

Kiran Kumar Eemani

Shivam Chawla

Santhosh Kumar Siripragada

Vijaya Janarthanam

Techniques for reducing write amplification in solid state storage are disclosed. A storage device includes single-level cell (SLC) and multi-level cell (MLCs) portions. A controller may allocate for storage in the SLC portions a sequential closed block pool for sequential data and a random closed block pool for random data. Responsive to certain conditions, the controller may relocate the sequential and random data from the respective sequential and random closed block pools to the MLC portions. The sequential data are relocated prior to the random data. Delaying relocation of random data reduces valid count at the relocation time, reducing write amplification and improving random reads.

Delaying random data relocation for reducing write amplification in storage devices

Methods and apparatus for management of thermal throttling in data storage devices are provided. One such data storage device includes a non-volatile memory (NVM), an always-on (AON) memory, and a processor coupled to the NVM and AON memory. The processor is configured to: receive an indication that a temperature of the data storage device exceeds a first temperature threshold, while the data storage device is in a powered-on state; store, responsive to the indication, status information of the data storage device in the AON memory; cause, responsive to the indication and the stored status information, the data storage device to enter a low power state wherein the only component of the data storage device that remains on is the AON memory; and restore, responsive to the data storage device resuming the powered-on state, the status information to the data storage device from the AON memory.

Management of thermal throttling in data storage devices

Aspects of a storage device including a memory and a controller are provided. The memory includes a volatile memory. The controller can determine that at least a portion in the volatile memory is a reusable region based on a host memory allocation from a host device. The controller also can calculate a size of the reusable region in the volatile memory. The controller also can perform one or more storage device operations in the reusable region of the volatile memory in response to the host memory allocation based on the calculated size of the reusable region. Thus, the controller may provide smart handling of host memory buffer allocation, thereby improving storage device read performance.

Host memory buffer allocation management

Aspects of a storage device include a memory comprising a plurality of memory locations each associated with a physical address, the memory configured to store a plurality of video frames received from a host device at the physical addresses, each of the video frames being associated with a logical address; and a controller configured to store in a partition of the memory the logical addresses for a subset of the video frames, the controller being configured to provide the host access to the partition to read the logical addresses during rapid playback of the video frames. Aspects of the host device include a processor configured to write the video frames to the storage device, to identify the subset of the video frames to the storage device, and during rapid playback, to access the storage device to read the logical address for each video frame in the subset.

Search time optimization in solid-state devices

After an ungraceful shutdown (UGSD) event, a data storage apparatus restores a fast boot-up table from a copy stored in a non-volatile memory (NVM), and receives a first read command from a host. The first read command includes a request to read data from a logical block address (LBA). The apparatus maintains a fast boot-up table that includes a plurality of entries, and each entry includes an LBA and an associated physical block address of the NVM. If the LBA is contained in the fast boot-up table, the apparatus determines a first physical block address associated with the LBA using the fast boot-up table. The apparatus reads data from the NVM at the first physical block address, prior to completing an initialization process of the data storage apparatus, and transmits the data read from the NVM to the host.

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Karnataka, India

Sridhar Prudvi Raj Gunda