Advanced Micro Devices Corporation

Rmi Corporation

Sridhar P Subramanian

John C Peck, Jr

Ranjit Joseph Rozario

Ravikrishna Cherukuri

Brian Hang Wai Yang

Scott Waldron

William Alexander Hughes

Benjamin T Sander

Wei-Han Lien

Gaurav Singh

Teik-Chung Tan

Michael S Quimby

Bruce A Loyer

Kiran B Kattel

Ali Kani

Niranjan Venigandla

Mark G Whitney

A packet transmit queue control system including a first data structure, a second data structure, a packet controller, and a port transmit controller is disclosed. The first data structure can include a plurality of linked-list data structures and can store unicast type packet pointers. The second data structure can include a plurality of first-in first-out (FIFO) structures and can store multicast type packet pointers. The packet controller can receive a first sequence of unicast and/or multicast type packets. The port transmit controller can provide a second sequence of the unicast and/or multicast type packets. Further, each of the plurality of FIFO structures can correspond to an output port of the system.

Method and apparatus for packet transmit queue control

A configurable lookup table system including a first controller coupled to a first lookup table and a second controller coupled to a second lookup table is disclosed. The first controller configures the first lookup table for a first type lookup, which can be a Layer 2 or Media Access Control (MAC) type. The second controller configures the second lookup table based on a mode determination. If in a first mode, the second lookup table can be configured for a second type lookup, which can be a Layer 3 or Internet Protocol (IP) type. If in a second mode, the second lookup table can be configured for the first type lookup. This approach provides an efficient scheme for controlling and using multiple internal lookup tables for a variety of product configurations.

Method and apparatus for providing internal table extensibility based on product configuration

A system includes a main memory device which stores information for translating a virtual address into a physical address in response to one of a plurality of processing devices. A memory control/interface device is coupled to the main memory device. The memory control/interface device, which may access the information stored in the main memory device, has a separate translation look-aside buffer for each processing device. Each translation look-aside buffer can buffer the information for use in translating in response to the respective processing device.

Distributed translation look-aside buffers for graphics address remapping table

A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation look-aside buffer cache has a plurality of translation look-aside buffer entries. Each translation look-aside buffer entry is operable to buffer information which may be accessed for use in translating a virtual address into a physical address. A least recently used pointer circuit is operable to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache. During operation, updates to the least recently used pointer circuit may be pipelined with corresponding accesses to the translation look-aside buffer cache.

Optimizing the translation of virtual addresses into physical addresses using a pipeline implementation for least recently used pointer

A circuit and method for stopping a clock tree while maintaining PLL lock. A clock circuit includes a locked loop circuit and a clock tree distribution network. The locked loop circuit receives an input clock signal and generates a PLL output clock depending upon a feedback signal. The clock tree is coupled to the locked loop circuit and conveys the PLL output clock to a plurality of clocked circuit elements. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network and selectively inhibits the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit provides the feedback signal, which represents a delayed version of the PLL output clock, during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree.

Circuit and method for stopping a clock tree while maintaining PLL lock

A control sequencer circuit issues a sequence of commands to logic devices synchronized to a response by a slave device to a command by a master device. In one instance, the control sequencer circuit is statically adjusted to the timing semantics of the acknowledgment signal of the slave device. The control sequencer circuit includes an event detector, a static sliding window, and a sequencer stage. The event detector receives an acknowledgment signal and a requester ID from a slave device and determines if it is the proper recipient. The static sliding window synchronizes the command sequence to the response by the slave device and adjusts for the timing semantics of the acknowledgment signal of the slave device. The control sequencer stage successively outputs active signals at each clock cycle, thereby generating the command sequence.

Optimized static sliding-window for ACK sampling

A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry includes a confidence counter. The confidence counter may be incremented each time another address in the pattern is detected, and thus may be indicative of the strength of the pattern (e.g., the likelihood of the pattern repeating). At a first threshold of the confidence counter, prefetching of the next address in the pattern (the most recent address plus the stride) may be initiated. At a second, greater threshold, a more aggressive prefetching may be initiated (e.g. the most recent address plus twice the stride). In some implementations, the prefetch mechanism including the stride detect table may replace a prefetch buffer and prefetch logic in the memory controller.

Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism

A computer aided design system and method for placing repeater buffers on a floor plan of an integrated circuit chip. The system includes a repeater placement tool that provides a near optimal placement of repeaters on the floor plan of a chip. The tool utilizes chip design netlist data indicating need for optimization to further decrease propagation delays in the design, wherein the data is manipulated by an algorithm which uses a combination of software programs that generate an approximate geometric placement of repeaters, that iteratively and heuristically improves the basic geometric layout, and that assigns, rule-based repeater type to each repeater, optimally determined to ensure that the strength, load, and other characteristics of the repeater buffers are correct, given the repeater location and the topology and loads of the nets.

System and method for automatic insertion and placement of repeater buffers on an integrated circuit floor plan

A gear box module or circuit can act as an interface for transferring data from a first clock domain to a second clock domain. The gear box circuit uses a level sensitive memory element coupled to an input selection circuit to receive data from logic in the first clock domain and provide the data to logic in the second clock domain. An input selection signal causes the selection circuit to select the input source for the level sensitive memory element, thereby allowing the proper signal to be provided as output to logic in the second clock domain. Additionally, the gear box can provide the proper output signal for logic in the second domain using circuitry to alternately mask the gear box output. The gear box receives control signals, including for example the input selection signal, from control circuitry. The logic in each clock domain does not have to be aware of the clock frequency on the other side of the gear box, nor does it need to be aware of the ratio of clock frequencies between clock domains. Consequently, the logic in each domain is simplified, the gear box circuit itself can be independent of the gear ratio (i.e., the ratio of clock frequencies), timing delays can be reduced, and metastability can be avoided.

Gear box for multiple clock domains

A method (,) of implementing a set of ordering rules for executing requests for access to a system memory (,) includes the steps of identifying a request status (,) for a new request for access to the system memory (,) and assigning a tag to the new access request (,) based on the status of the new request. A control circuit (,) inserts the new access request (,) into one of a read buffer (,) or a write buffer (,) at a specified location within one or the read or write buffers (,) based on the status of the new access request. When the new access request is enqueued (,) and sent to an arbitration circuit (,), the requests are executed in an order with another access request (,) from the other of the read or write buffer based on the request status and the tag of the new request.

Growing community of inventors

Sunnyvale, CA, United States of America

Sridhar P Subramanian