Intel Corporation

Other

Sridhar Muthrasanallur

Ohad Falik

Robert G Blankenship

Mahesh U Wagh

Jasmin Ajanovic

Debendra Das Sharma

Prashant Sethi

Ilan Pardo

David J Harriman

Mark B Rosenbluth

Scott Dion Rodgers

Anil Vasudevan

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Rajesh Sankaran Madukkarumukumana

Abraham Mendelson

Gilbert A Neiger

Kenneth C Creta

Avi Mendelson

Gideon Gerzon

Andrew V Anderson

Richard A Uhlig

Steven M Bennett

Erik C Cota-Robles

James B Crossland

Sebastian Schoenberg

Udo Steinberg

Avi (Abraham) Mendelson

Wilfred W Kwok

Yen-Cheng Liu

Shivnandan D Kaushik

Ganapati Srinivasa

Bahaa Fahim

Aaron T Spink

Lance E Hacking

Rajesh S Parthasarathy

Keshavan K Tiruvallur

Geeyarpuram N Santhanakrishnan

Luke Hood

Mohan J Kumar

Alon Naveh

Devadatta V Bodas

Anil Aggarwal

Rameshkumar G Illikkal

Mahesh K Kumashikar

Justin J Song

Rahul Pal

Nadav Bonen

Suresh Sugumar

Ramakrishna Huggahalli

Eric R Wehage

Sujith Thomas

Jayakrishna P S

Vishwanath Somayaji

Srinivas Pandruvada

Chitra Natarajan

Michael D Smith

Kedar J Karanje

Yogesh Vikram Marathe

Ankitkumar Pravinbhai Navik

Prashant Kodali

Jeff Wilder

Praveen Diwakar

Tvrtko Ursulin

Aravindan Muthukumar

Vipin Anand

Ohad Fallk

Ellezer Weissmann

Avi (Arraham) Mendelson

Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

Memory management to improve power performance

A system may include a graphics processing unit including a command counter. The system may also include a general-purpose processor to: in response to a detection of a timing signal, determine a count value of the command counter included in the graphics processing unit; determine a first threshold range of a plurality of threshold ranges that matches the determined count value of the command counter; select, based on the determined first threshold range, a first configuration profile of a plurality of configuration profiles for the graphics processing unit; and cause the graphics processing unit to use the selected first configuration profile. Other embodiments are described and claimed.

Configuration profiles for graphics processing unit

Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Posting interrupts to virtual processors

In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Providing common caching agent for core and integrated input/output (IO) module

A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn signal is sent over a dedicated wake-warn channel to indicate to the system component that the request is to arrive. Wake-warn signals cause a disabled clock to be ungated to an enabled state. The request is then sent to the system component.

Early wake-warn for clock gating control

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Atomic operations in PCI express

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Delivering interrupts directly to a virtual processor

Transaction layer packet formatting

An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a 'retry' event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the 'available' amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This &#x201c;available&#x201d; amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.

Apparatus and method to maximize buffer utilization in an I/O controller

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

Growing community of inventors

Puyallup, WA, United States of America

Sridhar Muthrasanallur