Intel Corporation

Google Inc.

Sridhar Lakshmanamurthy

Blaise B Fanning

Mikal Hunsaker

Michael T Klinglesmith

Robert P Adler

Joseph Murray

Rohit R Verma

Mark B Rosenbluth

Eran Tamari

Chen-Chi Kuo

Prashant R Chandra

Rohit Natarajan

Yim Pun

Gary J Lavelle

Lawrence B Huston

Jeen-Yuan Miin

Bijoy Bose

Debra Bernstein

Mohan Nair

Kar Leong Wong

Raymond Ng

Irwin J Vaz

Wilson Y Liao

Gilbert M Wolrich

Alok Kumar

Charles E Narad

Uday Ramakrishna Naik

Sanjeev Jain

Hugh Wilkinson

Ramadass Nagarajan

Robert De Gruijl

Hugh M Wilkinson, Iii

Kin-Yip Liu

Peter J Elardo

Senthil Nathan Arunachalam

Joydeep Ray

Norman Paul Jouppi

James D Guilford

Matthew James Adiletta

Martin Guy Dixon

Parthasarathy Ranganathan

Michael E Kounavis

Quoc V Le

Shreekant S Thakkar

Stephen S Pawlowski

Peter D MacWilliams

Jaroslaw Sydir

Kenneth D Shoemaker

Bruce L Fleming

Sheng Li

Raj S Yavatkar

Liqun Cheng

Suri B Medapati

Mason B Cabot

Alok Kumar Mathur

Daniel Stodolsky

Sameer Nanavati

Atul Kwatra

David Romano

Suketu R Partiwala

Harrick M Vin

Prashanth Kalluraya

Chang-Ming P Lin

Karthik Vaithianathan

Alpesh B Oza

Sami Yehia

Hugh Miller Wilkinson, Iii

Erik Karl Norden

Jeen-Xuan Miin

Dharmin Y Parikh

Edwin O'Yang

Subramanian Anand

Pun Yim

Mikal C Hunsaker

Mohan K Nair

Jeen-Yuan Min

Wilson Liao

Aspects of the disclosure are directed to a heterogeneous machine learning accelerator system with compute and memory nodes connected by high speed chip-to-chip interconnects. While existing remote/disaggregated memory may require memory expansion via remote processing units, aspects of the disclosure add memory nodes into machine learning accelerator clusters via the chip-to-chip interconnects without needing assistance from remote processing units to achieve higher performance, simpler software stack, and/or lower cost. The memory nodes may support prefetch and intelligent compression to enable the use of low cost memory without performance degradation.

Heterogeneous ML accelerator cluster with flexible system resource balance

In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

Method, apparatus and system for handling non-posted memory write transactions in a fabric

In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.

Sending packets with expanded headers

An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

Ultra low power architecture to support always on path to memory

In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Systems and an apparatus with a sideband interface interconnecting agents with at least one router

In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.

Providing multiple decode options for a system-on-chip (SoC) fabric

In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.

Supporting multiple channels of a single interface

In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express&#x2122; semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.

Providing error handling support to legacy devices

Aggregating completion messages in a sideband interface

According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

Providing a sideband message interface for system on a chip (SoC)

In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.

Common idle state, active state and credit management for an interface

In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Issuing requests to a fabric

Growing community of inventors

Sunnyvale, CA, United States of America

Sridhar Lakshmanamurthy