Xilinx, Inc.

Triscend Corporation

Nvidia Corporation

Altera Corporation

Jds Uniphase Corporation

Sridhar Krishnamurthy

Kamal Chaudhary

Shekhar Bapat

Bart Reynolds

Steven P Young

Jay T Young

Jeffrey V Lindholm

Trevor J Bauer

Mehrdad Eslami Dehkordi

Marvin Tom

Bernard J New

Anirban Rahut

Sankaranarayanan Srinivasan

Brian Fox

Brian Philofsky

Nicolas J Camilleri

Steven Winegarden

Kai Zhu

Damon McCormick

Priya Sundararajan

Sudip K Nag

Aaron Ng

Srinivasan Dasasathyan

Jean-Didier Allegrucci

Philip D Costello

Fung Fung Lee

Jay Chieh Chen

Grigor S Gasparyan

Ian L McEwen

Tetse Jang

Wilson Kaming Yee

Andrew W Lai

Binh Pham

Randy J Simmons

Andreas Papaliolios

Arye Ziklik

Rajat Aggarwal

Danesh Tavana

Vi Chi Chan

Kevin Chung

Cheng-I Chuang

Sanjeev Kwatra

Vincent L Tong

Gerardo Orlando

Vikas Kumar Agrawal

Tom Shui

Abhishek Joshi

Venkat Yadavalli

Vishal Suthar

Chi Keung Lee

David Richardson King

Chukwuweta Chukwudebe

Hasan Arslan

Teymour M Mansour

Raoul Badaoui

Mark Krumpoch

Arnaud Duthou

William R Troxel

Frank Mueller

Stanley S Yang

Ken Clauss

Peter Markou

Paul G Jacobsen

Scott A Guillaudeu

David R Freeman

Shrivathsa Bhargavravichandran

Umang Shah

Closing timing for a circuit design can include displaying, using a display device, a first region having a plurality of controls corresponding to a plurality of data sets generated at different times during a phase of a design flow for a circuit design, wherein each control selects a data set associated with the control, and displaying, using the display device, a second region configured to display a list of critical paths for data sets selected from the first region using one of the plurality of controls. Closing timing further can include displaying, using the display device, a third region configured to display a representation of a target integrated circuit including layouts for the critical paths of the list for implementations of the circuit design specified by the selected data sets.

Timing closure of circuit designs for integrated circuits

The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.

Generating clock trees for a circuit design

Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.

Placement and routing of clock signals for a circuit design

Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.

Clock region partitioning and clock routing

A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.

Hierarchical pushdown of cells and nets to any logical depth

A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.

Wide band deterministic interface

A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.

Implementing sub-circuits with predictable behavior within a circuit design

A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Latch based optimization during implementation of circuit designs for programmable logic devices

A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

A networking system may include a traffic generator. The traffic generator may include a scripting module configured to create a script. The traffic generator may execute the script to send and/or receive network messages within the networking system, which may help test one or more components of the networking system. The script may include one or more entries. An entry may be configured to instruct the traffic generator to send one or more network messages.

Systems and methods for generating network messages

A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.

Timing driven logic block configuration

Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, matching elements between a modified version of the circuit design and an implemented version of the circuit design are identified. Recommended placements for the matching elements are established based on placement information from the implemented version of the circuit design. An initial placement of the modified version of the circuit design is generated using the recommended placements. Timing-critical elements in the initial placement are identified. Locked placements for elements other than the timing-critical elements are established. An optimized placement of the modified version of the circuit design is generated using the locked placements.

Method and apparatus for directed physical implementation of a circuit design for an integrated circuit

A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit design on the target IC using a primary implementation of the plurality of implementations of the sub-circuit. The primary implementation of the sub-circuit can be selectively replaced with an alternate implementation of the sub-circuit selected from the plurality of implementations of the sub-circuit. The placed circuit design, including either the primary implementation or the alternate implementation of the sub-circuit, can be output.

Implementation of alternate solutions in technology mapping and placement

Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.

Methods of routing programmable logic devices to minimize programming time

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San Jose, CA, United States of America

Sridhar Krishnamurthy