Meta Platforms Technologies, LLC

Sridhar Gurumurthy Isukapalli Sharma

Drew Eric Wingard

Richard Lawrence Greene

Valerio Catalano

A system on a chip (SoC) includes a first subsystem, a second subsystem and a compression block connected to the first and second subsystems, wherein the compression block includes a decoder and an encoder. The compression block receives spill data generated by a compute element in one of the first and second subsystems, compresses the spill data using the encoder and stores the compressed spill data in a data block in local memory of one of the compute elements.

Lossless compression of large data sets for systems on a chip

The disclosure is directed to techniques for dynamically managing memory in mixed mode cache and shared memory systems. For example, a system on a chip (SoC) comprises: a plurality of memories, including a first memory and a second memory, where each of the memories includes one or more cache lines; a first subsystem comprising a first compute element and the first memory; a second subsystem comprising a second compute element and the second memory; and a memory control unit of the SoC comprising processing circuitry and configured to: configure a shared memory with one or more cache lines of at least one of the plurality of memories; and flush, based on one or more tag control bits for the one or more cache lines of the shared memory, data from the shared memory to a backend storage separate from the SoC.

Dynamic memory management in mixed mode cache and shared memory systems

A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.

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Palo Alto, CA, United States of America

Sridhar Gurumurthy Isukapalli Sharma