Arm Limited

Sridhar Cheruku

Nidhir Kumar

Sivaramakrishnan Subramanian

Sandeep Dwivedi

Manjunatha Govinda Prabhu

A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator.

Calibration of delay chains

An integrated circuitincludes a receiver circuitfor receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitrycouples an inputto a first node. Buffer circuitryis coupled between the first nodeand an outputcarrying the output signal Out. The conduction path circuitry comprises a first PMOS transistorand a second PMOS transistorconnected between the inputand the first node. A first NMOS transistoris connected between the inputand the first node. The gate of the second PMOS transistoris coupled to the outputto directly receive the output signal and thereby achieve rapid cut off of the charging of the nodewhen the input voltage rises beyond a certain level which switches the buffer circuitry

Receiver circuit with high input voltage protection

Calibration circuitryfor an off-chip driver circuitand/or an on-die termination circuitis provided using a parallel network of main transistors controlled by a N-bit calibration value. During the calibration operation, the N-bit calibration value is varied until a threshold impedance value is crossed by the combination of the main transistors. A rounding transistoris then used to determine which of the N-bit calibration values produces a combined impedance closest to the designed threshold impedance.

Reduced quantization error I/O resistor calibrator

An interface between first and second voltage domains is provided. A level shifter is configured to receive an input signal from the first voltage domain and to level shift the input signal to provide an output signal for passing to the second voltage domain. A control signal generator is configured to generate a second voltage domain control signal in dependence on at least one first voltage domain control signal from a controller in the first voltage domain. The level shifter is configured to be in a retention state when the second voltage domain control signal has a first value, such that its output signal is held constant even when the controller becomes not actively driven by the first voltage supply. The level shifter is configured to be in a transmission state when the second voltage domain control signal has a second value, wherein the output signal depends on the input signal.

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Bengaluru, India

Sridhar Cheruku