Qualcomm Incorporated

Sridhar Anumala

Santhosh Reddy Akavaram

Prakhar Srivastava

Chintalapati Bharath Sai Varma

Sonali Jabreva

Subrato Kumar De

Madhu Yashwanth Boenapalli

Ramacharan Sundararaman

Gaurav Singh

Ankur Bhattacharjee

Manish Garg

Sai Naresh Gajapaka

Mugdha Sanjay Patil

Radhakrishna Mugada

Sanjay Verdu

Dhananjayan Athiyappan

Nishanth Kumar

Bharani Bhuvanagiri

Khushboo Kumari

Various embodiments include methods implemented in a processor for management of cryptographic keys of an integrated cryptographic engine. Embodiments may include detecting a cryptographic key access control event, determining whether the cryptographic key access control event is for disabling cryptographic key access at a cryptographic key memory of the integrated cryptographic engine, disabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is for disabling cryptographic key access at the cryptographic key memory, and maintaining one or more cryptographic keys at the cryptographic key memory for which cryptographic key access is disabled. Embodiments may further include enabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is not for disabling cryptographic key access at the cryptographic key memory.

Approach to protect hardware managed integrated cryptographic engine keys efficiently while preventing data at rest attacks

A device includes a flash interface configured to be coupled to a flash memory device. The device also includes a host controller configured to select an interrupt level that indicates a threshold background operation status of a set of background operation statuses. The host controller is also configured to write the selected interrupt level to a register at the flash memory device to indicate, to the flash memory device, which of the set of background operation statuses are permissible sources of an interrupt from the flash memory device to the host controller.

Enhanced power management of flash memory device

Aspects relate to interrupting memory access during background operations of a memory device. In one example, a host for a memory device includes background operation circuitry configured to permit a background operation by a memory device. The host is coupled to the memory device through a bus. The host receives an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation. Memory access command circuitry is configured to receive a memory access command. The memory access command concerns reading or writing data to the memory device coupled to the host. The memory access command circuitry initiates a wait at the host for the memory access command, and sends the memory access command to the memory device in response to receiving the operation completed notification.

Interrupting memory access during background operations on a memory device

Systems and techniques are provided for wireless communications. A process can include determining that a quantity of a plurality of Mobile Terminated (MT) calls received within a first time period is greater than a first configured threshold. A process can include determining a subset of non-verified MT calls from the plurality of MT calls based on a call verification score for each respective MT call of the plurality of MT calls received within the first time period. A process can include determining that a quantity of non-verified MT calls included in the subset is greater than a second configured threshold. A process can include performing modem-level blocking based on determining a corresponding calling party identity associated with a non-verified MT call included in the subset.

Malicious call attack detection and mitigation

This disclosure provides systems, methods, and devices for memory systems that support exception event handling and reporting. In a first aspect, a method of exception event handling in a flash memory system includes a host memory controller receiving a response from the memory system, the response comprising user data, an indication that an exception event was encountered by the memory system, and information regarding the exception event encountered by the memory system; and transmitting an acknowledgement of receiving the indication that the exception event was encountered by the memory system. Other aspects and features are also claimed and described.

Exception event handling in flash memory system

Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures

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Hyderabad Telangana, India

Sridhar Anumala