International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Globalfoundries Inc.

Lenovo (singapore) Pte. Ltd.

Globalfoundries U.S. 2 LLC

Hitachi Global Technologies Netherlands B.v.

Sri Muthuthamby Sri-Jayantha

Hien Phu Dang

Arun Sharma

Vijayeshwar Das Khanna

Gerard McVicker

David L Questad

Charalampos Pozidis

Evangelos Stavros Eleftheriou

Isao Yoneda

Lorenzo Valdevit

Mark Alfred Lantz

Gordon James Smith

David John Russell

Naoyuki Kagami

Douglas Oliver Powell

Suresh Kumar

Kiyoshi Satoh

Karan Kacker

Michael A Gaynes

Jeffrey Donald Gelorme

James L Speidell

Frank Louis Pompeo

Thomas Edward Lombardi

Son K Tran

Marie-Claude Paquet

Yuzo Nakagawa

Jennifer V Muncy

Robert P Kuder, Ii

Daniel J Littrell

Tetsuo Ueda

Akira Tokizono

Nobuyuki Kitazaki

John Ulrich Knickerbocker

Giovanni Cherubini

Kerry Bernstein

Gareth Geoffrey Hougham

Hal Hjalmar Ottesen

Lawrence Shungwei Mok

Peter Vettiger

Sung Kwon Kang

Gerd K Binnig

Kenji Okada

Tatsuo Nakamoto

Jennifer V Muney

Thomas Albrecht

Mitsuro Ohta

Joseph Paul Kuczynski

Daniel C Edelstein

Michael S Gordon

Thomas R Albrecht

Kenneth Parker Rodbell

Qinghuang Lin

Christopher Vincent Jahnes

Roy Rongqing Yu

Arvind Kumar Sinha

Eric Andrew Joseph

Hiroyuki Miyazoe

Mark Kenneth Hoffmeyer

Robert L Wisnieff

Steven Alan Cordes

Vinod Kamath

Hideo Asano

Fu-Ying Huang

Steven Paul Ostrander

Mutsuro Ohta

Peter Jerome Sorce

Alok Kumar Lohia

Soojae Park

Tatsuya Sakai

Jung H Yoon

Kohji Serizawa

Mirei Hosono

Molly Smith

Kenneth F Latzko

Masayuki Takeuchi

Evangelos Elftheriou

Tatsuya Endoh

Vijayeshwar D Kharma

Vijaveshwar Das Khanna

Evan G Colgan

Gerard MoVicker

An organic substrate that has one or more layers. Each of the layers is made of one or more sub-patterns of conductive material disposed on a non-conductive material. The layers are divided into one or more tile subareas. A corresponding layer pair has a corresponding upper layer (with corresponding upper tile subareas) and a corresponding lower layer (with corresponding lower tile subareas) that are equidistant from and symmetric about a reference plane. Each corresponding upper tile subarea and the corresponding lower tile subarea are in a same vertical projection. A symmetric upper (lower) layout on the corresponding upper (lower) tile subarea replaces an original corresponding upper (lower) layer. The symmetric upper and lower layouts have one or more upper portions that have no electrical function but are partly responsible for making the symmetric lower layout and symmetric upper layout more thermo-mechanically symmetric and help reduce warp.

Warp mitigation using pattern-matched metal layers in organic substrates

A server node connection system uses two or more proximity sensors per server node to determine progressive, real time changes in wipe length for each individual connector on the node that is connected to an opposing header connector on header connected to a midplane of the server assembly/rack. The system is capable of scanning, monitoring, trending, and alarming.

Server node connector mating condition health monitoring and reporting

Heat is transferred to a cold plate from one or more subassemblies in an array of subassemblies in an electronic package. The cold plate has a thermally conductive cold plate substrate, a pressure header, a pressure passage, and one or more pressure connections. Each of the pressure connections connects through a housing opening to housing volume defined by a flexible housing in an encapsulated liquid thermal interface (LTI). The flexible housing is in physical and thermal contact with one of the subassemblies through a housing bottom and a top surface of one or more components in the subassembly. A thermally conductive fluid fills the housing volume, housing opening, pressure connections, pressure passage, and pressure header which are all in fluid communication along with one or more other connections, housing openings, and LTIs on other subassemblies. The system transfers heat from the subassemblies to the cold plate while maintaining a constant pressure/stress on each of the subassemblies. The system pressure on each of the subassemblies is equal. The system pressure can be controlled to a preloaded pressure to insure good electrical contact between components. Shear on the subassemblies is minimized by the LTIs.

Pressure controllable encapsulated liquid thermal interface

The substrate includes one or more bottom circuit (BC) layers disposed one upon another and one or more front circuit (FC) layers disposed one upon another. The FC layers are disposed on the BC layers. In some embodiments, there are one or more core layers disposed between the FC and BC layers. One or more soft zones are located within and penetrate through one or more of the FC layers. Each soft zone has a soft zone volume which is made of one or more component volumes located in each of one or more of the FC layers. Each soft zone component volume has a soft zone cross sectional area. The soft zone cross sectional areas are located inside a chip boundary projection. The chip boundary projection is a vertical projection of one or more sides of a semiconductor chip through the FC layers. The soft zone volume contains a soft zone material with a Young's modulus that is less than 100 GigaPascals (GPa). Alternative embodiments are presented with outside soft zones outside the chip boundary projection.

Stress mitigation in organic laminates

An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate. In some embodiments, a Shape Inversion Temperature (SIT) of the substrate is made equal to or above a reflow temperature.

Optimum warp in organic substrates

This invention is a laminated structure and methods used for electrically connecting one or more semiconductor chips to various external electrical connections where stresses within the laminated structure due to thermal cycle are reduced by adding conductive material to selected subareas of upper and lower layers in the structure such that the volume of conductive material in corresponding subareas is equal in amount and orientation within a threshold. This reduces differential stresses between the layers as temperature changes and accordingly reduces failures of materials and/or connections in the structure during manufacturing and operation.

Controlling warp in semiconductor laminated substrates with conductive material layout and orientation

Server node connnector mating condition health monitoring and reporting

A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body.

TIM strain mitigation in electronic modules

An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Method and apparatus for strain relieving surface mount attached connectors

Aspects relate to methods, systems, and computer program products for estimating future levels of solar power received at a sensor including receiving, by a processor, a first measured power value at a first time from the sensor, calculating a first value of a dynamic correction factor based on the first measured power value associated with the first time, applying the first value of the calculated dynamic correction factor to a power estimation model, generating a first power estimation value for a second time using the power estimation model, wherein the second time is later than the first time, receiving a second measured power value at the second time, and calculating a second value of a dynamic correction factor based on the second measured power value associated with the second time and the first value of the dynamic correction factor.

Real-time estimation of solar irradiation

A heat spreading lid including a lid body and a wing portion having a thermal interface material disposed on the wing portion such that the wing portion flexibly moves with the thermal interface material independently from the lid body.

Growing community of inventors

Ossining, NY, United States of America

Sri Muthuthamby Sri-Jayantha