Hughes Network Systems, LLC

Sri Bhat

Bala Subramaniam

Brandon Lasher

Yanlai Liu

Liming Qin

Mustafa Eroz

Liping Chen

Tony Huang

Seokho Kim

Krishnaraj Varma

Techniques are described for demodulating burst communications, such as for demodulating satellite beam-hopping communications in a demodulator of a very small aperture terminal (VSAT) satellite receiver. The demodulator includes a front-end and a sample/symbol domain processor. The front-end is configured to selectively operate in either of an adaptive mode or a freeze mode. During demodulation, the sample/symbol domain processor detects start of superframe (SOSF) and end of superframe (EOSF) locations to determine where each dwell time and non-dwell time begins and ends. During at least a portion or each dwell time, the front-end is set to operate in adaptive mode, in which the front-end uses feedback control from the sample/symbol domain processor to continuously adapt to timing and frequency of the received burst transmission. During at least the duration of each non-dwell time, the front-end is set to operate in freeze mode, in which adaptation of the front-end is frozen.

VSAT demodulator architecture for beam hopping satellite systems

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for channel bonding in an adaptive coding and modulation mode. In some implementations, a system receives packets of a data stream for transmission in a satellite communications system. The system determines a modulation and coding arrangement for the received packets. The system generates code blocks that include data from the packets of the data stream. The system assigns the generated code blocks for transmission on different carriers. One or more of the different carriers is operated in an adaptive coding and modulation mode to support multiple modulation and coding arrangements within a single carrier. The system transmits the code blocks on the different carriers using the determined one or more modulation and coding arrangements.

Channel bonding in an adaptive coding and modulation mode

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.

High speed interleaver/deinterleaver device supporting line rate, and method thereof

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are provided. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.

A method and apparatus allows single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the access table.

LDPC decoder design to significantly increase throughput in ASIC by utilizing pseudo two port memory structure

A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.

Growing community of inventors

Boyds, MD, United States of America

Sri Bhat