Juniper Networks, Inc.

Sreeram Veeragandham

Pradeep S Sindhu

Raymond Marcelino Manese Lim

Dennis C Ferguson

Rasoul Mirzazadeh Oskouy

Hann-Hwan Ju

Bjorn O Liencres

Nalini Agarwal

Jeff Zimmer

Rami Rahim

Michael M Y Hui

Kireeti Kompella

Jayabharat Boddu

David Skinner

Debashis Basu

Anurag P Gupta

Song Zhang

Chi-Chung Kenny Chen

Jorge Cruz-Rios

Thomas Michael Skibo

Jeffrey R Zimmer

Jia-Chang Wang

Srihari Shoroff

Michael Hui

A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

In-line packet processing

A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.

Separation of data and control in a switching device

A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Centralized memory allocation with write pointer drift correction

A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router.

Memory organization in a network device

Memory organization in a switching device

A system selectively drops data from a queue. The system includes queues that temporarily store data, a dequeue engine that dequeues data from the queues, and a drop engine that operates independently from the dequeue engine. The drop engine selects one of the queues to examine, determines whether to drop data from a head of the examined queue, and marks the data based on a result of the determination.

Systems and methods for congestion control using random early drop at head of buffer

A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine and the packet scheduler for transmitting a net data unit change value reflecting a change in packet size between an output of the packet scheduler and an output of the downstream processing engine.

Systems and methods for improving packet scheduling accuracy

A network device switches variable length data units from a source to a destination in a network. An input port receives the variable length data unit and a divider divides the variable length data unit into uniform length data units for temporary storage in the network device. A distributed memory includes a plurality of physically separated memory banks addressable using a single virtual address space and an input switch streams the uniform length data units across the memory banks based on the virtual address space. The network device further includes an output switch for extracting the uniform length data units from the distributed memory by using addresses of the uniform length data units within the virtual address space. The output switch reassembles the uniform length data units to reconstruct the variable length data unit. An output port receives the variable length data unit and transfers the variable length data unit to the destination.

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Sunnyvale, CA, United States of America

Sreeram Veeragandham