Texas Instruments Corporation

Sreeram Subramanyam Nasum

Kumar Anurag Shrivastava

Tarunvir Singh

Suvadip Banerjee

Scott Robert Summerfelt

Benjamin Stassen Cook

Thomas Dyer Bonifield

Peter Smeys

Subhashish Mukherjee

Somshubhra Paul

Kashyap Jayendra Barot

Niranjan Shankar

Jeffrey Alan West

Anant Shankar Kamath

Vijaylaxmi Gumaste Khanolkar

Prajkta Vyavahare

Kashyap Barot

Sudhir Komarla Adinarayana

Arun Adoni

Vijaylaximi Khanolkar

Sreenivasa S Mallia

A device includes a transformer having primary windings and secondary windings, and a transmit circuit coupled to the primary windings. The transmit circuit is configured to receive an input signal, and provide a carrier signal to the primary windings responsive to the input signal. The device also includes a receive circuit coupled to the secondary windings. The receive circuit is configured to receive the carrier signal from the secondary windings, and provide an output signal responsive to the carrier signal. The receive circuit includes a variable capacitor coupled in parallel to the secondary windings, and a spread spectrum modulation circuit configured to modulate a capacitance of the variable capacitor.

Spread spectrum modulation technique for isolation devices

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

Through wafer trench isolation between transistors in an integrated circuit

A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

Communication interface buffer with hot-swap protection

An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.

Leadframe capacitors

An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator.

Adaptive hysteretic control for a power converter

A low-dropout voltage system comprising a current supply with a transistor circuitry, a mode switch capacitor, and a decoupling capacitor, wherein the mode switch capacitor facilitates the low-drop voltage system to swiftly transition from a low mode with a minimal to no transient current output to a high mode with a transient current of about 6 mA by dynamically biasing the transistor circuitry while limiting a voltage or current draw from an external power source.

Low-dropout (LDO) voltage system

A digital isolator comprising a set of bipolar transistors and an inductor capacitor (LC) oscillator coupled to the set of bipolar transistors in series, wherein the LC oscillator is configured to be turned on and off based on the current applied to the set of bipolar transistors or the LC oscillator and generate a set of differential signals based on the current flowing through the set of bipolar transistors and mimicking the operational characteristics of an optocoupler.

Optocoupler emulating input stage for digital isolators

An encoding and transmitting system for a digital isolator system includes a transmitter for transmitting combined edge indicator signals through an isolation barrier, an encoder for generating the combined edge indicator signals based on first and second signals, a refresh clock generator for generating a refresh clock signal based on the first signal, and a refresh edge generator for masking at least a portion of the refresh clock signal, such that the portion of the refresh clock signal is not reflected in the second signal. The isolation barrier of the digital isolator system may be a capacitive isolation barrier for galvanically isolating a receiver from the transmitter. If desired, the refresh edge generator may include a refresh mask generator, one or more logic gates, and a glitch filter. A method of operating a digital isolator system is also described.

Architecture for resolution of data and refresh-path conflict for low-power digital isolator

An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having &#x2265;1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing &#x2265;2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.

Integrated circuit with inductors having electrically split scribe seal

A device includes a transformer that further includes a primary and a secondary windings. A switch is coupled to the primary winding, and this switch is controlled by the received digital input signal. An oscillator is further formed on the secondary winding where the oscillator oscillates in response to variations of the received input signal. A detector coupled to the oscillator will then detect the oscillations in response to the variations of the received input signal. Thereafter, the detector generates a digital output based on the detected oscillations.

Galvanic isolation in devices

An isolator chip includes a transmitter circuit coupled to provide differential output signals to respective first terminals of a first and a second capacitor and a receiver circuit coupled to receive the differential output signals from respective second terminals of the first and second capacitors. The transmitter circuit includes a voltage-clamping circuit coupled to receive an input signal and to provide a clamped signal, an oscillator coupled to receive the clamped signal and to provide the differential output signals, and a common mode transient immunity (CMTI) circuit that couples respective first terminals of the first and second capacitors to a lower rail responsive to the clamped signal being low.

Common mode transient immunity circuit for opto-isolator emulation

For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

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Sreeram Subramanyam Nasum