Qualcomm Incorporated

Sreenivasulu Reddy Chalamcharla

Dhamim Packer Ali

Daison Davis Koola

Alexander Gantman

Yanru Li

Dhaval Kanubhai Patel

Eric Taseski

Ruchi Parekh

Yugandhar Narayana

Ajay Iyengar

Tom C Wang

Sha Liu

Dhaval Patel

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the external component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

Boot time determination of calibration parameters for a component coupled to a system-on-chip

Various aspects are described herein. In some aspects, the disclosure provides a method of enabling a multicore framework in a pre-boot environment for a system-on-chip (SoC) comprising a plurality of processors comprising a first processor and a second processor. The method includes initiating, by the first processor, bootup of the SoC into a pre-boot environment. The method further includes scheduling, by the first processor, execution of one or more boot-up tasks by a second processor. The method further includes executing, by the second processor, the one or more boot-up tasks in the pre-boot environment. The method further includes executing, by the first processor, one or more additional tasks in parallel with the second processor executing the one or more boot-up tasks.

Multicore framework for use in pre-boot environment of a system-on-chip

A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.

Apparatus, system and method for autonomous recovery from failures during system characterization on an environment with restricted resources

Growing community of inventors

San Diego, CA, United States of America

Sreenivasulu Reddy Chalamcharla