Intel Corporation

Sreenivas Subramoney

Jayesh Gaur

Anant V Nori

Lihu Rappoport

Om Ji Omer

Hong Wang

Gurpreet Singh Kalsi

Zeev Sperber

Adi Yoaz

Richard Lewis Hudson

Stanislav Shwartsman

Saurabh Gupta

Tanay Karnik

Ronak Singhal

Dipan Kumar Mandal

Vedvyas Shanbhogue

Ali-Reza Adl-Tabatabai

Mauricio J Serrano

Belliappa Manavattira Kuttanna

Jared Warner Stark, Iv

Rahul Pal

Huichu Liu

David M Durham

Vinodh Gopal

Ian A Young

Wajdi K Feghali

Sergej Deutsch

Alaa R Alameldeen

Sasikanth Manipatruni

Christopher J Hughes

Uygar E Avci

Michael E Kounavis

Michael Lemay

Santosh Ghosh

Karanvir S Grewal

Yen-Cheng Liu

Yuval Amizur

Daniel Henry Morris

Deborah T Marr

Leor Banin

Robert S Chappell

Zvika Greenfield

Lance E Hacking

Mahesh K Kumashikar

Amit Kumar

Adrian C Moga

Suresh Srinivasan

Nir Dvorecki

Cormac Brick

Israel Diamand

Polychronis Xekalakis

Ragavendra Natarajan

Niranjan K Soundararajan

Adarsh Chauhan

Shankar Balachandran

Kamlesh R Pillai

Franck Sala

Niranjan Soundararajan

Lavanya Subramanian

Prathmesh Kallurkar

Vineeth Mekkat

Kaushik Vaidyanathan

Anirud Thyagharajan

Manjunath Shevgoor

Sourabh Alurkar

Prashant Laddha

Mainak Chaudhuri

Elad Shtiegmann

Joydeep Rakshit

Sumeet Bandishte

Aravinda Prasad

Biji George

Ayan Mandal

Ishwar Bhati

Nithiyanandan Bashyam

Srivatsa Rangachar Srinivasa

Avishaii Abuhatzera

Pooja Roy

Rahul Bera

Sriseshan Srikanth

Shengbo Xu

Michael D LeMay

Tejpal Singh

Chulong Chen

Saiveena Kesaraju

Supratik Majumder

Andy M Rudoff

Pavel I Kryukov

Ariel Sabba

Hanna Alam

Kamil Garifullin

Gopi Neela

Alexey Sivtsov

Swaraj Sha

Mahesh Mamidipaka

Pradyumna S Singh

Alexandr Titov

Anish N K

Srivatsava Jandhyala

Rakesh Ramesh

An embodiment of an apparatus comprises a hardware accelerator to perform a three-dimensional (3D) point cloud data access operation, and circuitry coupled to the hardware accelerator to control the hardware accelerator to perform the 3D point cloud data access operation in response to a request. Other embodiments are disclosed and claimed.

Point cloud adjacency-map and hash-map accelerator

Embodiments described herein are generally directed to maintaining contiguity of virtual to physical address mappings to exploit a contiguity-aware TLB. In an example, information regarding a migration set of one or more pages within a physical address space that have been identified for migration from a source tier of memory to a target tier of memory is received in which the physical address space comprises a first contiguous region of physical memory addresses and a VMA includes a second contiguous region of virtual memory addresses corresponding to the first contiguous region. It is determined whether the migration would break contiguity of a mapping maintained by a contiguity-aware TLB between pages of the first contiguous region and pages of the second contiguous region. Responsive an affirmative determination, discontinuities within the mapping resulting from the migration are minimized by intelligently increasing or decreasing the migration set.

Maintaining contiguity of virtual to physical address mappings to exploit contiguity-aware translation look-aside buffer hardware

An apparatus includes memory circuitry including a first data structure and prefetch circuitry that is coupled to the memory circuitry. The prefetch circuitry is to store, in the first data structure, a first subregion entry corresponding to a first subregion of a memory region allocated to a program. The first subregion entry is to include a plurality of delta values. A first delta value of the plurality of delta values represents a first distance between two cache lines associated with consecutive memory accesses within a second subregion of the memory region. The prefetch circuitry is further to detect a first memory access of a first cache line in the first subregion, identify prefetch candidates based on the first cache line and the plurality of delta values, and issue at least one prefetch request based on at least two of the prefetch candidates to be prefetched into a cache.

Region aware delta prefetcher

Techniques and mechanisms for a processor to determine an execution of instructions based on a prediction of a taken branch. In an embodiment, a first prediction unit generates each of multiple branch predictions in one cycle of successive branch prediction cycles. An indication of the branch predictions is provided to an execution pipeline, which prepares to execute an instruction based on the indication. Where a first one of the branch predictions is determined to be of a low confidence type, said first branch prediction is further indicated to a second prediction unit, which performs a second branch prediction based on the same branch instruction for which the first branch prediction was made. In another embodiment, the second prediction unit signals that a state of the execution pipeline is to be cleared, based on a determination that the first and second branch predictions are inconsistent with each other.

Device, method, and system to facilitate improved bandwidth of a branch prediction unit

Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

De-prioritizing speculative code lines in on-chip caches

Apparatus and method for leveraging simultaneous multithreading for bulk compute operations. For example, one embodiment of a processor comprises: a plurality of cores including a first core to simultaneously process instructions of a plurality of threads; a cache hierarchy coupled to the first core and the memory, the cache hierarchy comprising a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache; and a plurality of compute units coupled to the first core including a first compute unit associated with the L1 cache, a second compute unit associated with the L2 cache, and a third compute unit associated with the L3 cache, wherein the first core is to offload instructions for execution by the compute units, the first core to offload instructions from a first thread to the first compute unit, instructions from a second thread to the second compute unit, and instructions from a third thread to the third compute unit.

Method and apparatus for leveraging simultaneous multithreading for bulk compute operations

Embodiments are generally directed to techniques for accelerating neural networks. Many embodiments include a hardware accelerator for a bi-directional multi-layered GRU and LC neural network. Some embodiments are particularly directed to a hardware accelerator that enables offloading of the entire LC+GRU network to the hardware accelerator. Various embodiments include a hardware accelerator with a plurality of matrix vector units to perform GRU steps in parallel with LC steps. For example, at least a portion of computation by a first matrix vector unit of a GRU step in a neural network may overlap at least a portion of computation by a second matrix vector unit of an output feature vector for the neural network. Several embodiments include overlapping computation associated with a layer of a neural network with data transfer associated with another of the neural network.

Techniques for accelerating neural networks

Methods and apparatus relating to throttling a code fetch for speculative code paths are described. In an embodiment, a first storage structure stores a reference to a code line in response to a request to be received from a cache. A second storage structure to store a reference to the code line in response to an update to an Instruction Dispatch Queue (IDQ). Logic circuitry controls additional code line fetch operations based at least in part on a comparison of a number of ongoing speculative code fetches and a determination that the code line is speculative. Other embodiments are also disclosed and claimed.

Throttling code fetch for speculative code paths

Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.

Techniques to repurpose static random access memory rows to store a look-up-table for processor-in-memory operations

Disclosed Methods, Apparatus, and articles of manufacture to profile page tables for memory management are disclosed. An example apparatus includes a processor to execute computer readable instructions to: profile a first page at a first level of a page table as not part of a target group; and in response to profiling the first page as not part of the target group, label a data page at a second level that corresponds to the first page as not part of the target group, the second level being lower than the first level.

Methods and apparatus to profile page tables for memory management

System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

System, method, and apparatus for enhanced pointer identification and prefetching

Exemplary embodiments maintain spatial locality of the data being processed by a sparse CNN. The spatial locality is maintained by reordering the data to preserve spatial locality. The reordering may be performed on data elements and on data for groups of co-located data elements referred to herein as 'chunks'. Thus, the data may be reordered into chunks, where each chunk contains data for spatially co-located data elements, and in addition, chunks may be organized so that spatially located chunks are together. The use of chunks helps to reduce the need to re-fetch data during processing. Chunk sizes may be chosen based on the memory constraints of the processing logic (e.g., cache sizes).

Methods, apparatus, and articles of manufacture to reorder N-dimensional sparse data into groups of data elements that can be collocated in a memory

In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.

Segmented branch target buffer based on branch instruction type

Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

Instruction and micro-architecture support for decompression on core

An embodiment of an integrated circuit may comprise a core, a front end unit coupled to the core to decode one or more instruction wherein the front end unit includes a first decode path, a second decode path, and circuitry to: predict a taken branch of a conditional branch instruction of the one or more instructions, decode a predicted path of the taken branch on the first decode path, determine if the conditional branch instruction corresponds to a hard-to-predict conditional branch instruction and if the second decode path is available and, if so determined, decode an alternate path of a not-taken branch of the hard-to-predict conditional branch instruction on the second decode path. Other embodiments are disclosed and claimed.

Alternate path decode for hard-to-predict branch

Growing community of inventors

Bengaluru, India

Sreenivas Subramoney