Deep Vision, Inc.

Nvidia Corporation

Aurobindo Pharma Limited

Sreenivas Reddy

Mohamed Shahim

Raju Datla

Suresh Kumar Vennam

Lava Kumar Bokam

Sameek Banerjee

Sivakumaran Meenakshisunderam

John George Mathieson

Venugopala Chokkasandra Jayaramareddy

Vikas Bansal

Chandrashekhar Shriram Kandi

Kiran Kumar Kathireddy

A method includes: dequeuing a signal primitive from a signaling command queue in the set of command queues, the signal primitive pointing to a waiting command queue; in response to the signal primitive pointing to the waiting command queue, incrementing a number of pending signal primitives in the signal-wait counter matrix; dequeuing a wait primitive from the waiting command queue, the wait primitive pointing to the signaling command queue; in response to the wait primitive pointing to the signaling command queue, accessing the register to read the number of pending signal primitives; in response to the number of pending signal primitives indicating at least one pending signal primitive: decrementing the number of pending signal primitives; and dequeuing an instruction from the waiting command queue; and dispatching a control signal representing the instruction to a resource.

System and method for maintaining dependencies in a parallel process

A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.

Processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process

System and method for queuing commands in a deep learning processor

A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; and electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.

Pharmaceutical compositions comprising an antidiabetic agent as an active agent are provided. The present invention relates to pharmaceutical compositions comprising linagliptin or a pharmaceutically acceptable salt thereof as an active agent. The present invention also relates to process of preparation of pharmaceutical compositions comprising linagliptin or a pharmaceutically acceptable salt thereof. The present invention also relates to method of administering the compositions comprising linagliptin to a subject in need thereof.

Pharmaceutical compositions of linagliptin and process for preparation thereof

According to an aspect of the present invention, the communication between processors and peripheral controllers is provided using packets. In an embodiment, the access requests are specified according to a common format such that all the information required for performing each access request is included in a single packet and sent to the peripheral controller. The peripheral controller performs the access request on the external device and generates a response. According to another aspect, the packet format enables the peripheral controller to send responses, requests originating from the external devices and interrupt requests. According to yet another aspect, the packets from processors are first stored in a random access memory (RAM) and a DMA controller retrieves the packets and delivered to the respective peripheral controllers.

Communication between a processor and a controller

In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.

Growing community of inventors

Hyderabad Telangana, India

Sreenivas Reddy