Intel Corporation

Sreenivas Mandava

Brian S Morris

John H Crawford

Kuljit Singh Bains

Raj K Ramanujan

Vedaraman Geetha

Theodros Yigzaw

John V Lovelace

Suneeta Sah

Massimo Sutera

Henk G Neefs

Roy M Stevens

Ted Rossin

Mathew W Stefaniw

Mohan J Kumar

Wei P Chen

Rajat Agarwal

Bill Nale

Ashok Raj

Wei Wu

Sarathy Jayakumar

Jing Ling

Deep K Buch

John G Holm

Debaleena Das

Andrew M Rudoff

Kjersten E Criss

Jongwon Lee

Ronald N Story

Hsing-Min Chen

Anders Fogh

Vaibhav Singh

A memory chip includes row hammer threat detection circuitry. The memory chip includes an output. The memory chip includes backpressure signal generation circuitry coupled between the row hammer detection circuitry and the output. The backpressure signal generation circuitry is to generate a backpressure signal to be sent from the output in response to detection by the row hammer threat detection circuitry of a row hammer threat.

Method and apparatus for memory chip row hammer threat backpressure signal and host side response

Initialization of a memory can have different phases, first initializing a portion of memory for BIOS (basic input/output system) and initializing other portions of memory while the BIOS is operating. The initialization of the memory can be performed by the error scrub engine. In a first mode of operation, the scrub engine can initialize memory locations, then transition to performing scrub operations.

Deferred ECC (error checking and correction) memory initialization by memory scrub hardware

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

A probabilistic scheme that uses temperature to reload an LFSR at runtime introduces randomness to prevent row hammer attacks. In one example, a memory controller includes input/output (I/O) interface circuitry to receive memory access requests from a processor. A linear feedback shift register (LFSR) in the memory controller is shifted in response to receipt of a memory access request to a target address. The shift register is compared a value in the LFSR with a pre-determined value. If the value in the LFSR is equal to the predetermined value, a refresh is triggered to one or more neighboring addresses of the target address. The LFSR is reloaded with one of multiple seeds based on a temperature (for example, from an on-die thermal sensor, a DIMM sensor, and/or other temperature). Selecting one of multiple seeds based on temperature on the fly makes the scheme unpredictable and robust against row hammer.

Temperature-based runtime variability in victim address selection for probabilistic schemes for row hammer

A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.

Fast boot up memory controller

An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.

Apparatus and method for system physical address to memory module address translation

Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

Techniques for probabilistic dynamic random access memory row repair

Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Techniques for determining victim row addresses in a volatile memory

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Los Altos, CA, United States of America

Sreenivas Mandava