Texas Instruments Corporation

Sreenath Narayanan Potty

Jawaharlal Tangudu

Jasbir Singh Nayyar

Vivek Singhal

Jaiganesh Balakrishnan

Sthanunathan Ramakrishnan

Rajesh Kumar Mittal

Mudasir Shafat Kawoosa

Sashidharan Venkatraman

Sunil Chomal

Pankaj Gupta

Aswath Vs

Ajai Paulose

Girish Nadiger

Sriram Murali

Sundarrajan Rangachari

Neeraj Shrivastava

Nagarajan Viswanathan

Mukesh Kumar

Chandrasekhar Sriram

Himanshu Varshney

Sumanth Reddy Poddutur

Raju Kharataram Chaudhari

Divyeshkumar Mahendrabhai Patel

Karthik Khanna Subramani

Divyansh Jain

Ankur Jain

Mahesh Ravi Varma

Kapil Kumar

Shabbar Abbasi Vejlani

Crest factor reduction circuitry includes: a peak neighborhood analyzer; peak detection circuitry and a controller. The peak neighborhood analyzer is configured to: receive an input signal; analyze the input signal to determine whether a peak larger than a target threshold is expected within an interval; and provide a first control signal responsive to determining that a peak larger than the target threshold is expected within the interval. The controller is configured to: receive the first control signal; and gate a clock or data to the peak detection circuitry responsive to the first control signal.

Power efficient crest factor reduction

An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

High order nonlinearity estimation of radiofrequency analog-to-digital converters

A personal navigation device includes a correlator for processing GNSS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.

Memory optimized GNSS correlator

A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

Non-linearity correction

An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy.

Interleaved ADC with estimation of DSA-setting-based IL mismatch

An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Method and apparatus for test time reduction using fractional data packing

A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.

Analog-digital compatible re-sampling

A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.

Phase shifted coarse/fine clock dithering responsive to controller select signals

Systems and methods for enabling scan testing of device-under-test (DUT) are disclosed. In an embodiment, a test system for scan testing the DUT, including P scan input ports and Q scan output ports, includes tester and adapter module. Tester operates at clock frequency Fand includes M tester Input/Output (I/O) ports for providing M scan inputs and N tester I/O ports for receiving N scan outputs at F. Adapter module is coupled to tester and configured to receive M scan inputs at Fand, in response, provide P scan inputs at clock frequency Fto P scan input ports, and to receive Q scan outputs at Ffrom Q scan output ports and, in response, provide N scan outputs at Fto N tester I/O ports, where ratio of M to P equals ratio of N to Q, and where each of M, N, P and Q are positive integers.

Scan throughput enhancement in scan testing of a device-under-test

An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements. Each packing element includes k number of flip-flops. Each flip-flop of the k number of flip-flops receives a scan output of the M scan outputs and a phase-shifted scan clock of the k number of phase-shifted scan clocks, and generates a slow scan output of the kM slow scan outputs.

Handling slower scan outputs at optimal frequency

A system can include a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC) signal and an image of the signal tone in the discrete frequency domain representation of the IADC signal and determines a correlation between the signal tone and the image of the signal tone, a power of the signal tone and a power of the image of the signal tone. The system can also include a frequency domain estimator that determines an instantaneous frequency domain mismatch profile estimate based on the correlation between the signal tone and the image of the signal tone. The system can further include an averaging filter that averages the instantaneous frequency domain mismatch profile estimate over time to provide a frequency domain mismatch profile estimate.

Mismatch profile

A mismatch corrector can include a correction path comprising a plurality of parallel branches that each includes a correction filter that applies a respective one of a plurality of time domain filter coefficients that corresponds to a function of a mismatch profile of an interleaved analog-to-digital (IADC) signal on the IADC signal. The mismatch corrector can also include a delay path that delays the IADC signal by a predetermined number of samples to provide a delayed version of the IADC signal. The mismatch corrector can further include a summer to subtract an output of each correction filter from the delayed version of the IADC signal to generate a corrected IADC signal.

Mismatch corrector

A system can include a close-in tone control configured to detect a set of close-in tones of an interleaved analog to digital converter (IADC) signal and output a trigger signal in response to the detection. The system can also include a close-in tone mismatch estimator configured to determine a correlation and a power estimate for the set of close-in tones in the IADC signal in response to the trigger signal.

Growing community of inventors

Trivandrum, India

Sreenath Narayanan Potty