Qualcomm Incorporated

Sreekanth Modaikkal

Kumar Samir Saurabh

Chun Wang

Anitha Madugiri Siddaraju

Rahul Gulati

Kalyan Thota

Paul Christopher John Wiercienski

John Chi Kit Wong

Gary Arthur Ciambella

Vishnuvardhan Prodduturi

Naveenchandra Shetty Brahmavar

Samson Kim

Kit Fong Ng

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a power efficient display architecture. A display processor may obtain an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor may drive a first display via a first controller of a first DPU based on the indication. The display processor may drive a second display via a controller of a second DPU if the UC is to be displayed at the first resolution, or drive the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution.

Power efficient display architecture

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for synchronized dual eye variable refresh rate update for a VR display. A display processor obtains an indication of a synchronous flush or an asynchronous flush with respect to a first DPU and/or a second DPU. The display processor determines whether a first flush operation and/or a second flush operation is available at a time instance, where the first flush operation and the second flush operation are associated with the first DPU and/or the second DPU. The display processor performs, based on a VSync instance, the first flush operation and/or the second flush operation based on whether the first flush operation and/or the second flush operation are available at the time instance and based on the indication of the synchronous flush or the asynchronous flush.

Synchronized dual eye variable refresh rate update for VR display

The present disclosure relates to methods and apparatus for data processing, e.g., a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.

Methods and apparatus for data content integrity

This disclosure describes examples for generating image content based on both a color value and a dither value that is to be applied. When a color value for the current pixel is the same as the color value for a previous pixel, and a dither value that is to be applied to the current pixel is the same as the dither value that was added to the previous pixel, a display processor may output the output color value for the previous pixel as the output color value for the current pixel.

Dither spatial noise aware redundancy bypass

In an example, a method for tile-based processing by a display processor may include reading first foreground tile data of a foreground image from a first memory space. The method may include storing the read first foreground tile data into a second memory space. The method may include reading first background tile data of a background image from the first memory space. The method may include storing the read first background tile data into a third memory space. The method may include reading a subset of data of the first foreground tile data from the second memory space. The method may include reading a subset of data of the first background tile data from the third memory space.

Growing community of inventors

Bengaluru, India

Sreekanth Modaikkal