International Business Machines Corporation

Sreekala Anandavally

Anand Haridass

Gerard M Salem

Bodo Hoppe

Richard Frank Rizzolo

Sean Michael Carey

Diyanesh B C Vidyapoornachary

Divya Kumudprakash Joshi

Paul Jacob Logsdon

William Rurik

A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests ('LBIST') trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Error injection for timing margin protection and frequency closure

Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Core diagnostics and repair

Multi-core diagnostics and repair using firmware and spare cores

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Karnataka, India

Sreekala Anandavally