Samsung Electronics Co., Ltd.

Sreedharan Sreejith

Praseeth K Sreedharan

Jack C Wybenga

Pradeep Dinkar Samudra

A packet routing system is provided that comprises a processor, a component, a resource map and a resource map manger. The component classifies an incoming packet of a user session. The resource map identifies a plurality of resources used to process the incoming packet. The resource map manager determines an availability of at least some of the resources and based on the availability either promote processing the incoming packet or drop the incoming packet.

Method and system for packet traffic congestion management

An apparatus for use in a first packet switching device that transmits outgoing data packets to a second packet switching device over N heterogeneous data links. The first packet switching device comprises N packet queues for storing outgoing data packets. The apparatus selects one of the N heterogeneous data links to transmit a first outgoing data packet. The apparatus comprises a controller that calculates a packet delay value for each one of a subset of S of the N heterogeneous data links. The packet delay (PD) value for each data link is determined as a function of i) a propagation delay (D) of the data link; ii) a packet size (PS) of the first outgoing data packet; iii) a queue size (QS) of a packet queue associated with the data link; and iv) a bandwidth (BW) of the data link.

Apparatus and method for queuing delay-sensitive packets for transmission on heterogenous links

A dynamic scheduling system is provided that comprises a processor, a polling task, a work task, and a scheduler assistant task. The polling task is configured for execution by the processor, wherein the polling task executes during a first CPU time window and sleeps during a second CPU time window. The work task is configured for an execution during the second CPU time window. The scheduler assistant (SA) task has an execution state to indicate to the polling task a status of the execution of the work task to the polling task. The SA task is configured to run if the work task runs to completion within the second CPU time window.

Dynamic application scheduler in a polling system

A system is provided that includes a hardware forwarding engine that routes data packets. The system also comprises a processor coupled to the hardware forwarding engine, the processor having a software forwarding engine that routes data packets. If data packets are forwarded from the hardware forwarding engine to the software forwarding engine, the hardware forwarding engine provides route lookup results for at least some of the data packets forwarded to the software forwarding engine.

Methods and systems for routing packets with a hardware forwarding engine and a software forwarding engine

In a distributed router containing routing nodes connected by a switch fabric, an input-output processor for use in the routing nodes. The input-out processor comprises: 1) an input interface controller for receiving incoming data packets from N input links; 2) an output interface controller for transmitting outgoing data packets to the switch fabric via a first uplink and a second uplink. Each of the N input links is assigned to one of the first and second uplinks so that incoming data packets from each input link are transmitted to the switch fabric by the assigned one of the first and second uplinks. The input-out processor also comprises 3) a load balancing controller for i) determining first and second uplink traffic levels on the first and second uplinks, ii) determining a difference between the first and second uplink traffic levels, iii) comparing the difference to a predetermined threshold, and, iv) in response to a determination that the difference exceeds the predetermined threshold, reassigning at least one input link from the uplink having the greater uplink traffic level to the uplink having the lesser uplink traffic level.

Router using measurement-based adaptable load traffic balancing system and method of operation

A head of line (HOL) blocking count value, which is directly proportional to the committed traffic load for traffic flow through an output port within a multi-stage switch mesh, is computed for a path by adding the values associated with all output ports within the path. In selecting a route, all paths from the source to the destination are identified and sorted by head of line blocking count value. Rather than selecting a path based on traffic load, the path having the lowest head of line blocking count value and sufficient capacity for the requested traffic is selected, with selection between paths having equal head of line blocking count values being made based on traffic load.

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Santa Clara, CA, United States of America

Sreedharan Sreejith