Cisco Technology, Inc.

Intel Corporation

Altera Corporation

Sreedhar Ravipalli

Mohammed Ismael Tatar

David Delano Ward

David Richard Barach

Naader Hasani

Shishir Gupta

Shahin Habibi

Md Altaf Hossain

Ankireddy Nalamalpu

Aravind Raghavendra Dasu

Mahesh K Kumashikar

Stephen S Chang

Nishit Patel

Teng Wang

Naveed Zaman

Raghucharan Boddupalli

Luan Bui

Jing Miao

Dinesh Kotti

Ranjini Rajeevan

Rakesh Cheerla

Martin Horne

Ratan Ramchandani

A circuit system includes an accelerator circuit and a compute circuit. The accelerator circuit generates a request in response to receiving packets of data. The accelerator circuit generates an indication of a low power state based on a reduced number of the packets of data being received. The compute circuit performs a processing operation for the accelerator circuit using the packets of data in response to receiving the request. The compute circuit comprises a power management circuit that decreases a supply voltage in the compute circuit and decreases a frequency of a clock signal in the compute circuit in response to the indication of the low power state from the accelerator circuit.

Techniques for power management in compute circuits

Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.

Chained command architecture for packet processing

A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.

Stacked die network interface controller circuitry

In connection with an access of content from a cache, a snoop request can be sent to one or more remote cache devices to determine if any other cache has a copy of the content. A link between the cache and the remote cache devices can include a snoop bypass device. The snoop bypass device can monitor content cached by the one or more remote devices on a cache line or coarser granularity. The snoop bypass device can respond to the snoop request with a negative indication based on a coarser granularity tracking of content of the one or more remote cache devices.

Management of cache use requests sent to remote cache devices

One embodiment performs longest prefix matching operations in one or more different manners that provides packet processing and/or memory efficiencies in the processing of packets. In one embodiment, a packet switching device determines a set of one or more mask lengths of a particular conforming entry of a multibit trie or other data structure that matches a particular address of a packet via a lookup operation in a mask length data structure. A conforming entry refers to an entry which has less than or equal to a maximum number of different prefix lengths, with this maximum number corresponding to the maximum number of prefix lengths which can be searched in parallel in the address space for a longest matching prefix by the implementing hardware. The packet switching device then performs corresponding hash table lookup operation(s) in parallel in determining an overall longest matching prefix for the particular address.

Longest prefix matching providing packet processing and/or memory efficiencies in processing of packets

In one embodiment, a hierarchical scheduling system including multiple scheduling layers with layer bypass is used to schedule items (e.g., corresponding to packets). This scheduling of items performed in one embodiment includes: propagating first items through the hierarchical scheduling system and updating scheduling information in each of the plurality of scheduling layers based on said propagated first items as said propagated first items propagate through the plurality of scheduling layers, and bypassing one or more scheduling layers of the plurality of scheduling layers for scheduling bypassing items and updating scheduling information in each of said bypassed one or more scheduling layers based on said bypassing items. In one embodiment, this method is performed by a particular machine. In one embodiment, the operations of propagating first items through the hierarchical scheduling system and bypassing one or more scheduling layers are done in parallel.

Hierarchical scheduling system with layer bypass including updating scheduling information of a scheduling layer for each item whether or not it bypasses the scheduling layer

Growing community of inventors

Cupertino, CA, United States of America

Sreedhar Ravipalli