Adv Antest Corporation

Srdjan Malisic

Chi Yuan

Duane Champoux

Seth W Craighead

Jenny Chen

Edmundo De La Puente

Mei-Mei Su

Michael Frank Jones

Linden Hsu

Rebecca Qiu

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester includes a direct access device (DAX) interface that prevents corruption of DUTs. In one exemplary implementation, the tester isolates testing of a particular CXL enabled DUT from undesirable interference and corruption. The tester can prevent inappropriate writing over the DUT's memory. The DUTs reside in the separate per-device space of a Linux operating system rather than an extension of memory space. One of the plurality of DUTs can be a CXL typememory expander device. In one exemplary implementation, the direct access device (DAX) interface creates a unique DAX instance for each individual DUT included in the plurality of DUTs

Systems and methods utilizing DAX memory management for testing CXL protocol enabled devices

Efficient and effective testing systems and methods are presented. In one embodiment, a testing system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing. In one exemplary implementation, the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.

CXL protocol enablement for test environment systems and methods

Efficient and effective testing systems and methods are presented. In one embodiment, a system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester is configured to enable hot add of one of the plurality of DUTs without interfering with testing of the other DUTS. In one exemplary implementation, the DUTs are memory devices and the DUTs can operate as extended memory. An added DUT can be automatically recognized by a host in a way that is transparent to users (e.g., BIOS can direct detection of characteristics of an added DUT, etc.). The tester automatically can direct the hot add in response to a user trigger.

Management of hot add in a testing environment for DUTs that are CXL protocol enabled

Automatic test equipment (ATE) configured to test devices under test (DUTs) can include a host device tester, one or more load boards, and one or more host bus adapters (HBAs). The host device tester does not support odd sector sizes and/or non-standard sector sizes. The one or more load boards can be communicatively coupled to the host device. The one or more HBAs can be communicatively coupled between respective load boards and one or more respective devices under test (DUTs). The one or more load boards can be configured to communicate with respective HBAs using one or more first communication protocol interfaces. The one or more HBAs can be configured to communicate with the respective DUTs using one or more second communication protocol interfaces. The HBAs can be configured to translate commands and data between the host device tester and the one or more DUTs that support odd sector size or non-standard sector size.

Automatic test equipment architecture providing odd sector size support

A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT. The tester system also includes a memory coupled to the processor and including a plurality of buffers, the plurality of buffers organized into a first-in-first-out (FIFO) memory queue including a buffer front end and a buffer back end, the plurality of buffers operable to receive the test pattern data from the processor at the buffer front end, a direct memory access (DMA) engine coupled to the memory and operable for reading data out of the buffer back end and supplying test pattern data to the DUT, a buffer table for maintaining a buffer sequence within the plurality of buffers and for maintaining vacancy and occupancy information regarding the plurality of buffers, and driver hardware coupled to the DMA engine and operable to receive the test pattern data and for driving the test input signals to the plurality of DUTs.

Memory queue operations to increase throughput in an ATE system

Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.

Lockless log and error reporting for automatic test equipment

Embodiments of the present invention can provide an extended NVMe driver that supports exercising virtual functions (and related physical functions) of a DUT without using a VM or hypervisor. In this way, the amount of memory and processing resources used for testing NVMe SSDs can be significantly reduced, and a large number of DUTs (e.g., up to 16 DUTs) can be tested in parallel independently. In other words, each DUT is tested in isolation, as if is the only device being tested, and there are no race conditions or competition for resources between workloads during testing.

Systems and methods for testing virtual functions of a device under test

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Systems and methods for parallel testing of multiple namespaces located in a plurality of devices under test

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs. In one exemplary implementation, the controller directs a portion of sideband testing of a plurality of DUTs concurrently.

Flexible sideband support systems and methods

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing flexible and independent parallel testing across the plurality of DUTs. In one exemplary implementation, the tester generates and manages workloads independently for DUTs included in the plurality of DUTs. The DUTs can be memory devices the tester is configured to test different memory spaces in parallel. The different memory spaces can have various implementations (e.g., included in the plurality of DUTs, different memory spaces are within one of the DUTs included in the plurality of DUTs, etc.). Workloads can be generated based upon individual characteristics of the DUTS and managed separately. The testing can include performance testing. (e.g., bandwidth testing, latency testing, error testing, etc.).

Systems and methods for testing cxl enabled devices in parallel

A method for testing using an automated test equipment (ATE) comprises transmitting instructions for executing tests on a device under test (DUT) from a tester processor to a queue communicatively coupled with the tester processor and a Field Programmable Gate Array (FPGA), wherein the tester processor is configured to determine a hardware acceleration mode from a plurality of hardware acceleration modes for executing tests on the DUT. Further, the hardware acceleration mode is configured to distribute functionality for generating commands and data between the tester processor and the FPGA, wherein in at least one hardware acceleration mode the tester processor is configured to generate commands for testing the DUT and the FPGA is configured to generate data for testing the DUT. The method also comprises accessing the instructions in the queue, translating the instructions into commands associated with testing the DUT and transmitting the commands to the DUT.

Software directed firmware acceleration

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, an enhanced auxiliary interface test system comprises a load board, testing electronics, controller, and memory mapped interface. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics is configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics. The memory mapped interface is configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel.

Enhanced auxiliary memory mapped interface test systems and methods

Multiple name space test systems and methods

An automated test equipment (ATE) system comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor, wherein the system controller is operable to transmit instructions to the tester processor. The tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT), wherein the DUT supports an arbitrary sector size, and wherein software layers on the tester processor perform computations to be able control data flow between the tester processor and sectors of arbitrary size in the DUT.

Growing community of inventors

San Jose, CA, United States of America

Srdjan Malisic