Nxp B.v.

Freescale Semiconductor,inc.

Koninklijke Philips Corporation N.v.

Stmicroelectronics S.a.

Other

Stmicroelectronics S.r.l.

Stmicroelectronics (crolles 2) Sas

Srdjan Kordic

Janos Farkas

Sebastien Petitdidier

Alain Inard

Cindy Goldberg

Céline Roussel

Joaquin Torres

Philippe Gayet

Meindert Martin Lunenborg

Lynne M Michaelson

Eric Gerritsen

Kevin E Cooper

Maria Luisa Calvo-Munoz

Brigitte Descouts

Pascale Motte

Theodore Carambeeris

Silvio Del Monaco

Jean-Philippe Jacquemin

Kevin Cooper

Olivier Dubreuil

Jan Van Hassel

Veronique De-Jonghe

Jan Van-Hassel

A method of selective formation of silicide on a semiconductor wafer, wherein the metal layer is deposited over the entire wafer prior to application of the SiProt mask such that any etching of the mask does not cause any surface deterioration of the silicon wafer.

Silicide formation on a wafer

Silicon wafers and the like are cleaned using new scrubber-type apparatus in which measures are taken to compensate for differential cleaning of the central region of the wafer by: using rotary brushes having one or more non-contact portions arranged in the section thereof that faces the central region of the substrate, or toggling the relative position of the wafer and the rotary brushes, or directing cleaning fluid(s) preferentially towards the central region of the wafer. Another aspect of the invention provides scrubber-type cleaning apparatus in which the rotary brushes are replaced by rollers (). A web of cleaning material () is interposed between each roller and the substrate. Various different webs of cleaning material may be used, e.g. a length of tissue, a continuous loop of cleaning material whose surface is reconditioned on each cleaning pass, adhesive material provided on a carrier tape, etc.

Apparatus for cleaning of circuit substrates

A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterized in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alkylthiol, sulfonate, methanosulfonate, and cyanide, and salts thereof. 

Capping layer formation onto a dual damescene interconnect

The present invention relates to a cost saving liquid-treatment unit (). According to the invention, a control unit (), which is connected to an input port of a control valve (), is adapted to set, in dependence on the evaporation rate of a treatment liquid on the substrate at the given or desired temperature of the substrate and/or at the given or desired pressure of a gaseous ambient atmosphere at the substrate, a number of dispense pulses to be applied to the substrate for the liquid treatment, a respective pulse duration of individual dispense pulses, and respective dispense-interruption time spans between the individual dispense pulses. This way, the use of treatment liquid is reduced to a minimum amount, thus reducing costs for providing and cleaning treatment liquid.

Pulsed chemical dispense system

The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element () between a first and a second metal structure. The fabrication comprises providing an ambient environment adjacent to an interconnect surface region of a substrate that is suitable for allowing growth of at least one metal dendrite between the first and second metal structures, and initiating and sustaining self-assembly of a metal structure comprising at least one metal dendrite in the interconnect surface region between the first and second metal structures by irradiating the pn junction with photons of an energy suitable for creating free charge carriers in the first and second doped substrate regions and thus creating an electric potential difference between the first and second metal structures, which is suitable for electrolysis of metal from at least one of the first and second metal structures.

Fabrication of self-assembled nanowire-type interconnects on a semiconductor device

The invention provides a method and a device for determining the temperature of a semiconductor substrate. A resonance circuit () is provided on the semiconductor substrate and is formed by a junction capacitor () and an inductor (). The substrate is placed on a holder and the resonance circuit () is irradiated with electromagnetic energy of an electromagnetic field () generated by a radiation device (). A resonance frequency of the resonance circuit () is determined by detecting an effect of the resonance circuit () on the irradiated electromagnetic field (), and a temperature of the semiconductor substrate is determined as a function of the resonance frequency. The method and device according to the invention provide for a more accurate determination of the temperature of the semiconductor substrate due to an increased sensitivity to the temperature of the junction capacitor ().

Semiconductor substrate temperature determination

A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material.

Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereor, and material for coupling a dielectric layer and a metal layer in a semiconductor device

A system for removing particles from a polishing pad to improve the efficiency of the removal of material by the polishing pad as part of a chemical-mechanical polishing process, the system comprising a polishing pad; a fluid dispenser arranged to dispense a fluid on the polishing pad; and removal means, wherein the removal means include a heater for increasing the temperature of the fluid dispensed on the polishing pad, and/or voltage means for coupling the polishing pad to a voltage source for repelling charged particles from the polishing pad surface while the fluid dispenser is dispensing the fluid on the polishing pad.

System and method for removing particles from a polishing pad

A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated.

Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and passivating coupling material comprising multiple organic components for use in a semiconductor device

Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and material for coupling a dielectric layer and a metal layer in a semiconductor device

A process for fabricating an integrated electrical circuit comprises the formation and then the removal of conducting inserts. Components of the electrical circuit are incorporated into insulating materials superposed on top of a substrate. The process makes it possible to provide an exclusion volume around certain components sensitive to electrostatic coupling, while giving each insulating material a planar surface at the end of a polishing step.

Process for fabricating an electrical circuit comprising a polishing step

An electrical connection device between two conducting tracks of an integrated circuit comprises a first conducting connection between the two tracks. The device further comprises an additional interface of one of the two tracks, different from the interface of the track with the first connection and different from the lateral interface of the track with an insulating material parallel to the flow direction of the electric current in the track. The additional interface is placed at some distance from the first connection which is substantially less than the width of the track. The additional interface may be obtained by placing at least a second conducting connection between the two tracks, or by placing at least one rib in the track, or by placing notches on at least one of the faces of the track.

Electrical connection device between two tracks of an integrated circuit

A process produces at a predetermined metallization level at least one metal track ( ) within an intertrack dielectric material ( ). The process includes the steps of etching the intertrack dielectric material ( ) so as to form a cavity ( ) at the position of the track, depositing a conducting barrier layer ( ) in the cavity ( ), filling the cavity ( ) with copper, and depositing a silicon nitride layer ( ) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi ( ) during the diffusion of the silicon from the silicon nitride layer ( ).

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Biviers, France

Srdjan Kordic