Sandisk Technologies Inc.

Sravanti Addepalli

Sridhar Yadala

Ravindra Arjun Madpur

Hitoshi Miwa

A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.

Duty cycle and skew correction for output signals generated in source synchronous systems

Techniques for trimming an on chip ZQ calibration resistor are disclosed. The on chip ZQ calibration resistor alleviates the need for an external ZQ calibration resistor. The on chip ZQ calibration resistor allows for a faster ZQ calibration. The trimming of on chip ZQ calibration resistor may be used to account for process variation. A correction mechanism may be used to account for temperature variation. Some of the circuitry that is used for ZQ calibration is also used for trimming the on-chip calibration resistor. This circuitry may include operational amplifiers, current mirrors, transistors, etc. The dual use of the circuitry can eliminate offset errors in an operational amplifier. The dual use can eliminate current mirror mismatch. Therefore, the trimming accuracy may be improved. The dual use also reduces the amount of circuitry that is needed for trimming the on chip ZQ calibration resistor. Thus, transistor count and chip size is reduced.

On chip ZQ calibration resistor trimming

A non-volatile storage system includes an impedance code calibration circuit. The device has a first variable impedance circuit and a second variable impedance circuit coupled to a calibration node. The device has a control circuit configured to access a previous impedance code for a previous impedance calibration and to divide the previous impedance code into a main impedance code and a remainder impedance code. The control circuit is configured to perform a search for a new impedance code starting with the main impedance code applied to the first variable impedance circuit while maintaining the remainder impedance code to the second variable impedance circuit. The control circuit is configured to add the final impedance code for the first variable impedance circuit with the remainder impedance code to produce a new impedance code for the impedance calibration.

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Bengaluru, India

Sravanti Addepalli