International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Globalfoudries Inc.

Spyridon Skordas

Wei Lin

Kevin R Winstel

Mukta G Farooq

Douglas C La Tulipe, Jr

Tuan Anh Vo

Lawrence Alfred Clevenger

Deepika Priyadarshini

Leathen Shi

Robert R Young, Jr

Michael Rizzolo

Benjamin David Briggs

Subramanian Srikanteswara Iyer

John Anthony Fitzsimmons

Leigh Anne H Clevenger

Maryam Ashoori

Justin A Canaperi

Daniel C Edelstein

Son Van Nguyen

Stephen McConnell Gates

Jason Scott Orcutt

Donald Francis Canaperi

Erdem Kaltalioglu

Jean-Olivier Plouchart

James John Kelly

Troy Lawrence Graves-Abe

Joyeeta Nag

John W Golz

Dale Curtis McHerron

Richard C Johnson

Alex Richard Hubbard

Allan Ward Upham

Pooja R Batra

Da Song

Kangguo Cheng

Anthony K Stamper

Bing Dang

Sanjay C Mehta

Edmund Juris Sprogis

Marc Adam Bergendahl

Richard Paul Volant

Gauri V Karve

Cornelius Brown Peethala

Eric D Perfecto

Cornelia K Tsang

Raghuveer Reddy Patlolla

Shidong Li

Sarah Huffsmith Knickerbocker

Richard Francis Indyk

Ravi K Bonam

Brown Cornelius Peethala

Matthew T Shoudy

Cody John Murray

Nitin H Parbhoo

Binglin Miao

Jonathan E Faltermeier

A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

Resist patterned redistribution wiring on copper polyimide via layer

A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

Paint on micro chip touch screens

A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.

Oxide-bonded wafer pair separation using laser debonding

An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.

Selective etching of silicon wafer

Copper (Cu)-to-Cu bonding techniques for high bandwidth interconnects on a bridge chip attached to chips which are further attached to a packaging substrate are provided. In one aspect, a method of forming an interconnect structure is provided. The method includes: bonding individual chips to at least one bridge chip via Cu-to-Cu bonding to form a multi-chip structure; and bonding the multi-chip structure to a packaging substrate via solder bonding, after the Cu-to-Cu bonding has been performed, to form the interconnect structure including the individual chips bonded to the at least one bridge chip and to the packaging substrate. A structure formed by the method is also provided.

Cu&#x2014;Cu bonding for interconnects on bridge chip attached to chips and packaging substrate

A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.

Cognitive system for automatic risk assessment, solution identification, and action enablement

Devices and methods for granting requests for authorization using data of devices associated with requestors are disclosed. A method includes: receiving, by a computing device, a request for authorization; receiving, by the computing device, identification information for at least one device of a requestor; determining, by the computing device, a risk score using the received identification information for the at least one device of the requestor; and in response to the risk score exceeding a predetermined threshold, the computing device granting the request for authorization.

Granting requests for authorization using data of devices associated with requestors

A wafer bonding method includes placing a first wafer on a first bonding framework including a plurality of outlet holes around a periphery of the first bonding framework. A second wafer is placed on a second bonding framework that includes a plurality of inlet holes around a periphery of the second bonding framework. The first bonding framework is in overlapping relation to the second bonding framework such that a gap exist between the first wafer and the second wafer. A gas stream is circulated through the gap between the first wafer and the second wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the first wafer and the second wafer.

Gas-controlled bonding platform for edge defect reduction during wafer bonding

Communication source identifier verification system mechanisms are provided. The mechanisms receive communication information for a communication initiated between a source communication system and a destination communication system. The communication information comprises a source identifier and a local device identifier signature specifying zero or more local device identifiers of devices local to the source communication system. The mechanisms retrieve valid device identifier information for an authorized communication source corresponding to the identifier of the source communication system. The mechanisms execute a verification operation that verifies whether the source identifier is validly associated with the source communication system based on the retrieved valid device identifier information and the local device identifier signature. The mechanisms send a verification notification along with the communication information, in response to results of executing the verification operation, to the destination communication system.

Caller identity verification based on unique multi-device signatures

A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

Semiconductor device including built-in crack-arresting film structure

A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.

Advanced chip to wafer stacking

Growing community of inventors

Troy, NY, United States of America

Spyridon Skordas