Seoul National University

Skhynix Inc.

Soyeong Shin

Deog-Kyoon Jeong

Han-Gon Ko

Jiheon Park

Jung Hun Park

KwangHoon Lee

A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.

Clock transfer circuit including a semiconductor device for compensating delay fluctuation

A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.

Semiconductor device for compensating delay fluctuation and clock transfer circuit including the same

Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver () generating waveform including data to be transmitted; and an FFE driver block () connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.

Transmitter having merged FFE and XTC, and transmission method thereof

A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.

Growing community of inventors

Uiwang-si, South Korea

Soyeong Shin