Marvell Asia Pte., Ltd.

Cavium, Inc.

Sowmya Hotha

Weihuang Wang

Premshanth Theivendran

Srinath Atluri

Chia-Hsin Chen

Saurabh Shrivastava

Heeloo Chung

Srinath Alturi

A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.

Barrel compactor system, method and device

A new approach contemplates systems and methods to support control of power consumption of a memory on a chip by throttling port access requests to the memory via a memory arbiter based on a one or more programmable parameters. The memory arbiter is configured to restrict the number of ports being used to access the memory at the same time to be less than the available ports of the memory, thereby enabling adaptive power control of the chip. Two port throttling schemes are enabled&#x2014;strict port throttling, which throttles the number of ports granted for memory access to be no more than a user-configured maximum throttle port number, and leaky bucket port throttling, which throttles the number of ports granted for the memory access down to be within a range based on a number of credit tokens maintained in a credit register.

System and methods for on-chip memory (OCM) port throttling for machine learning operations

Barrel compactor system, method and device having cell combination logic

Growing community of inventors

Cupertino, CA, United States of America

Sowmya Hotha