Intel Corporation

Souvik Ghosh

Jack T Kavalieros

Willy Rachmady

Anand S Murthy

Matthew V Metz

Kimin Jun

Ashish Agrawal

Siddharth Chouksey

Ryan Keech

Jessica M Torres

Koustav Ganguly

An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Self-aligned interconnect structures and methods of fabrication

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Beaverton, OR, United States of America

Souvik Ghosh