International Business Machines Corporation

Globalfoundries U.S. Inc.

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

George Mason University

Elpis Technologies Inc.

Souvick Mitra

Robert J Gauthier, Jr

JunJun Li

Christopher Stephen Putnam

Tom C Lee

Rahul Mishra

John B Campi, Jr

Mujahid Muhammad

Michel J Abou-Khalil

You Li

Alain F Loiseau

James Paul Di Sarro

Tsung-Che Tsai

Mickey H Yu

Meng Miao

Anindya Nath

Nathan D Jack

Wei Liang

Robert Russell Robison

Junjun Li

Mahmoud A Mousa

Shunhua Thomas Chang

Jie Zeng

Andreas Scholze

Sagar Premnath Karalkar

Anthony K Stamper

Theodorus E Standaert

William R Tonti

Chengwen Pei

Rajendran Krishnasamy

Hongmei Li

Prantik Mahajan

Milova Paul

Michael J Abou-Khalil

Terence B Hook

Kirk David Peterson

Shesh Mani Pandey

Akram Ali Salman

Ephrem G Gebreselasie

Andrew A Turner

Nathaniel R Chadwick

Ruchil Kumar Jain

Zhiqing Li

Jun Jun Li

Rainer Thoma

Dimitris E Ioannou

Robert Gauthier

Robert J Gauthier

Dimitrios K Kontos

Harsh Shah

Alain François Loiseau

Yang Yang

Vishal Ganesan

Ajay

Ajay Ajay

Tsai Tsung-Che

Manjunatha Prabu

Christopher S Putnam

Mahmoud Mousa

Jr Robert Gauthier

The present disclosure relates to a structure including a trigger element within a semiconductor-on-insulator (SOI) substrate, and a silicon controlled rectifier (SCR) under a buried insulator layer of the SOI substrate. The trigger element is between an anode and a cathode of the SCR.

Vertically integrated SCR structure with SOI-based raised trigger element

Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a first well and a second well in the semiconductor substrate. The first and second wells have a first conductivity type. The structure further comprises a third well and a fourth well in the semiconductor substrate. The third and fourth wells have a second conductivity type, the third well includes a portion that overlaps with the first well, and the fourth well includes a portion that overlaps with the second well.

Electrostatic discharge protection devices

Structures for an electrostatic discharge device including a silicon-controlled rectifier and methods of forming a structure for an electrostatic discharge device that includes a silicon-controlled rectifier. The structure includes a first well in a semiconductor substrate, a second well and a third well in the first well, and a fourth well in the first well. The first well has a first conductivity type, and the second well and the third well have the first conductivity type. The fourth well positioned in a lateral direction between the second well and the third well, and the fourth well has a second conductivity type opposite to the first conductivity type. The second well, the third well, and the fourth well are positioned in a vertical direction between the first well and a top surface of the semiconductor substrate.

Electrostatic discharge protection devices including a silicon-controlled rectifier

Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

Integrated circuit structure with diode over lateral bipolar transistor

The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.

Vertically stacked diode-trigger silicon controlled rectifier

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

Fin-based and bipolar electrostatic discharge devices

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.

Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well

A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

Operating voltage-triggered semiconductor controlled rectifier

Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

Symmetric bi-directional silicon-controlled rectifier for electrostatic discharge protection

Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P− closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

Semiconductor-controlled rectifier with low trigger voltage for electrostatic discharge protection

Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.

Silicon-controlled rectifiers in a silicon-on-insulator technology

Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes a first well and a second well in a semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. The structure further includes a first terminal having a doped region that has a portion in the first well, and a second terminal including a second doped region that has a portion in the first well and a third doped region in the second well. The first and second doped regions have the second conductivity type, the third doped region has the first conductivity type, and the second doped region is positioned in a lateral direction between the first doped region and the third doped region.

Silicon-controlled rectifiers for electrostatic discharge protection

A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

Electrostatic discharge clamp structures

Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes first and second wells in the semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite to the first conductivity type. First and second conductor layers are positioned on the semiconductor substrate. The first conductor layer partially overlaps with the first well, and the second conductor layer partially overlaps with the second well. A third doped region, which has the second conductivity type, is laterally positioned in the semiconductor substrate between the first and second conductor layers.

Silicon-controlled rectifiers for an electrostatic discharge protection device

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Essex Junction, VT, United States of America

Souvick Mitra