Fujitsu Corporation

Souta Kusachi

Yuichiro Ajima

Jouji Kunii

Masaki Ukai

Go Sugizaki

Tomoyuki Okawa

Satoshi Nakagawa

Kuniki Morita

A transfer apparatus for performing transmission and reception of data using a plurality of lanes includes: a transmission control unit configured to, upon receiving a transmission instruction for performing a data transfer in a redundant mode in which the same data is transferred using a plurality of lanes, output transmission data as first data and second data without renegotiation with another transfer apparatus; a first transmission unit configured to transmit the first data output by the transmission control unit via a first lane; and a second transmission unit configured to transmit the second data output by the transmission control unit via a second lane.

Transfer apparatus and transfer method

A data communication device communicating with other devices via multiple communication paths includes a transmission unit and a reception unit. The transmission unit is configured to receive a packet containing header information and data, to output the header information to each of the communication paths, to divide the data into multiple data pieces, and to output the data pieces to the respective communication paths. The reception unit is configured to receive header information and a data piece for each of the communication paths, and to reconstruct a packet from the header information and the data piece received from each of the communication paths. In reconstructing the packet, the reception unit adjusts, for each of the communication paths, output timing of the data piece, based on the header information.

Data communication device, arithmetic processing device, and control method of data communication device

A transmission device includes, a receiver that receives availability information of each of a plurality of first transmission paths, and a transmitter that divides data into a plurality of transmission blocks, groups the plurality of transmission blocks into a plurality of slices, each of the plurality of slices include a distinct subset of the plurality of transmission blocks, when the availability information indicates that each of the plurality of first transmission paths has an error occurrence below a threshold value, transmits a different one of the plurality of slices to each of the plurality of first transmission paths.

Transmission device, transmission reception system and control method for transmission reception system

A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.

System having processor and I/O controller

A memory control apparatus, a memory control method and an information processing system are disclosed. Fetch response data retrieved from a main storage unit is received, while bypassing a storage unit, by a first port in which the received fetch response data can be set. The fetch response data retrieved from the main storage unit, if unable to be set in the first port, is set in a second port through the storage unit. A transmission control unit performs priority control operation to send out, in accordance with a predetermined priority, the fetch response data set in the first port or the second port to the processor. As a result, the latency is shortened from the time when the fetch response data arrives to the time when the fetch response data is sent out toward the processor in response to a fetch request from the processor.

Memory control apparatus, memory control method and information processing system

A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

Growing community of inventors

Yokohama, Japan

Souta Kusachi