Intel Corporation

Sourav Chakravarty

Mark T Bohr

Ranjith Kumar

Barbara A Chappell

Andrew W Yeoh

M Clair Webb

Quan Shi

Mauro J Kobrinsky

Ruth Amy Brain

R Scott List

Mohiuddin M Mazumder

Marni Nabors

Dmitry Messerman

Tai-Hsuan Wu

Yaakov Ben-Noon

Eli Chiprout

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Multi version library cell handling and integrated circuit structures fabricated therefrom

An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

Power shared cell architecture

Embodiments of the present invention provide a method, apparatus and system for inductance modeling. According to some exemplary embodiments, a method for inductance modeling may include determining a plurality of two-dimensional mutual inductance values corresponding to a designated victim within a geometrical event and a plurality of designated attackers, respectively. Other embodiments are described and claimed.

Method, apparatus and system for inductance modeling in an electrical configuration

A closed-loop based timing signal distribution architecture includes at least one signal source coupled to a signal path disposed in a closed loop arrangement to facilitate generation of a standing wave signal within the signal path. In one embodiment, at least one receiver is coupled to the signal path to generate at least one digital clock signal based upon the standing wave signal.

Method of signal distribution based on a standing wave within a closed loop path

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Portland, OR, United States of America

Sourav Chakravarty