Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sourabh Sankule

Dinesh Kumar Agarwal

Piyush Girish Sagdeo

Srinivasan Seetharaman

Amit Kumar Sharma

Chris Yip

Nikhil Arora

Chetan Agrawal

Lovleen Arora

Sameer Hiware

Mohan Dunga

Gautam Ashok Dusija

Niles Yang

Anubhav Khandelwal

Pitamber Shukla

Vimal Kumar Jain

Vijay Sivasankaran

Mikhail Palityka

Avinash Sharma

Hitesh Golechchha

Chris Nga Yee Yip

Vishal Sharma

Darshan Pagariya

The disclosure relates in some aspects to a design for a data storage apparatus with a non-volatile memory that includes a block of memory comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a failure in a first sub-block. The second sub-block is then marked, in response to a failure detection in the first sub-block, with an initial designation as an unusable sub-block, and a test of the second sub-block is performed to determine a usability of the second sub-block. Based on the test, the second sub-block is then marked with a second designation that is one of a tested usable sub-block or a tested unusable sub-block.

Systems and methods for evaluating integrity of adjacent sub blocks of data storage apparatuses

Data blocks may be optimized and managed in a mixed mode that utilizes a single-level cell (SLC) mode in combination with higher-density memory modes to promote full block utilization and to increase overall cycles of the data blocks. A data block cycling process in the mixed mode can place a data block in a higher-density memory mode that includes a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode, if the SLC cycle count of the data block is relatively higher as compared to other data blocks. Similarly, in the mixed mode, a data block may be placed in the SLC mode to store parity data or intermediate data if the corresponding TLC cycle count is relatively higher than other data blocks. Data clocks cycles may also be evenly distributed in the mixed mode, thereby balancing the mixed mode usage across all data blocks.

Mixed mode block cycling for intermediate data

A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.

Data storage device and method for power on reset and read error handling

Aspects of a storage device including a memory and a controller are provided. The memory includes non-volatile memory and volatile memory. The controller may determine whether first data is available at a system-level memory location during a first programming stage of a two-stage programming sequence. The controller may read the first data from the system-level memory location when the page data is available at the system-level memory location. Alternatively, the controller may read the first data from the non-volatile memory when the page data is not available at the system-level memory location. Thus, the controller may perform a first programming operation associated with the first programming stage using the first data, thereby improving memory programming performance of the storage device.

User controlled data-in for lower and middle page in MLC-fine QLC memories

Aspects of a storage device including a controller are provided which identifies a bad, open block that causes subsequent erase operations to fail in closed blocks due to charge leakage following a previous program operation in the open block. Each time the controller programs an open block, the controller attempts to erase a plurality of closed blocks following each programming of the open block. When the closed blocks fail to erase, the controller determines whether a number of consecutive erase failures after programming the open block meets a threshold, after which the controller re-attempts to erase the closed blocks. After a successful re-attempt, the controller stores a list of open blocks in memory. In response to repeating these steps a number or plurality of times, the controller stores multiple lists of open blocks in memory, and identifies the single common open block between the multiple lists as a bad block.

System to identify aggressor blocks causing back to back erase failure

A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.

Storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint

Aspects of a storage device are provided which allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. The storage device includes a memory configured to store data and a plurality of control pages. Each of the control pages includes a plurality of logical addresses associated with the data. A controller is configured to receive from a host device a plurality of read commands associated with a sequence of the control pages. The controller is further configured to identify and store a control page pattern based on the sequence of control pages and to predict one or more of the control pages from one or more of the other control pages in the sequence in a subsequent plurality of read commands.

Pattern tracking for efficiently predicting control pages

Aspects of a storage device including a controller are provided which recovers misidentified bad blocks that fail to erase due to charge leakage from a previously programmed open block. The controller programs an open block, and attempts to erase a plurality of closed blocks following the programming of the open block. When the closed blocks fail to erase, the controller marks the closed blocks as bad blocks. The controller then determines whether a number of consecutive erase failures after programming the open block meets a threshold, in response to which the controller resets a die including the closed blocks and reattempts to erase the closed blocks. The controller then unmarks as bad blocks the closed blocks which successfully erased in response to the re-attempt.

Erase operation reattempt to recover misidentified bad blocks resulting from consecutive erase failures

A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.

System handling for first read read disturb

The disclosure relates in some aspects to a read scrub design for a non-volatile memory that includes a block comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a trigger event associated with a read command performed on the first sub-block. A target sub-block test is then performed in response to a detection of the trigger event to determine whether to add the first sub-block to a read scrub queue. If the first sub-block is added to the read scrub queue, a sister sub-block test is then performed to determine whether to add the second sub-block to the read scrub queue.

Sub block mode read scrub design for non-volatile memory

Techniques are provided for maintaining threshold voltages of non-data transistors in a memory device. The memory device has a stack comprising alternating horizontal conductive layers and horizontal dielectric layers. A control circuit is configured to test a threshold voltage criterion of non-data transistors in response to a trigger condition being met with respect to an erase of a data memory cells in a first tier of the stack. The control circuit is configured move valid data out of a data memory cells in a second tier of the stack in response to a determination that the threshold voltage criterion is not met. The control circuit is configured to adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells such that the threshold voltage criterion is met.

Transistor threshold voltage maintenance in 3D memory

Systems and methods are disclosed for executing access commands for a data storage device. A data storage device receives first data to be written to a plurality of dies/non-volatile memory arrays. The data storage device transfers a first metapage of the first data to the plurality of dies/non-volatile memory arrays. The data storage device also programs the first metapage to a first metablock of the plurality of dies and programs the first metapage to a second metablock of the plurality of dies/non-volatile memory arrays. The data storage device further transfers a second metapage to the plurality of dies/non-volatile memory arrays. Programming the first metapage to the first metablock may be simultaneous with transferring the second metapage to the plurality of dies/non-volatile memory arrays.

Systems and methods for controlling metapage storage on data storage devices

A solution for combining a portion of data from a block of single level cells to a block of multi-level cells. The solution includes identifying word lines with only valid data and word lines with non-valid data in a selected block of single level cells, copying data from word lines with valid data to a destination block of multi-level cells and copying data from word lines in the selected block of single level cells with non-valid data to a separate compaction block of single level cells. The system includes a first controller module configured to scan for word lines with only valid data and pass a bitmap identifying valid and invalid word lines to a second controller module. The second controller module is configured to perform on-chip combining of data from valid word lines, and copy data from invalid data word lines to a compaction block of single level cells.

Growing community of inventors

Karnataka, India

Sourabh Sankule