Intel Corporation

Sourabh Alurkar

Sreenivas Subramoney

Anant V Nori

Vineeth Mekkat

Manjunath Shevgoor

Shankar Balachandran

Elad Shtiegmann

Stanislav Shwartsman

Karthikeyan Avudaiyappan

System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

System, method, and apparatus for enhanced pointer identification and prefetching

A method for supporting a plurality of requests for access to a data cache memory ('cache') is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.

Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput

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Sunnyvale, CA, United States of America

Sourabh Alurkar