Samsung Electronics Co., Ltd.

Soung-Hoon Sim

Jong-Hoon Jung

Gyu-Hong Kim

Tae-Joong Song

Chan-Ho Lee

Jung-Min Choi

Jae-Seung Choi

Hyun-Su Choi

In-Gyu Park

Hyo-Sang Lee

A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

Negative voltage generator and semiconductor memory device

A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group.

Static memory device and static random access memory device

A method of compiling a memory for layout by computation includes inputting memory specification, determining a disposition structure of input/output pads with reference to the memory specification, and creating a layout of the memory in accordance with the determined disposition structure of the input/output pads. A memory includes a plurality of memory banks, a plurality of row decoders and a plurality of input/output pads. Each of the plurality of row decoders is arranged between two memory banks adjacent to each other in a row direction. The plurality of row decoders are configured to selectively activate word lines based on row address signals input from an external source. Each row decoder receives row address signals altering a permutation in accordance with a size of the memory banks.

Memories, memory compiling systems and methods for the same

A flash memory can operate by providing a first voltage level from a row decoder to a wordline associated with a cell of a flash memory device. An address provided to the row decoder is decoded during an erase mode operation of the flash memory. The first voltage level is increased to a second voltage level provided from the row decoder to the wordline responsive to determining that the wordline is not selected by the address during the erase mode operation.

Methods and devices for increasing voltages on non-selected wordlines during erasure of a flash memory

An integrated circuit memory device includes a source line and a memory cell array that includes n memory cells that are connected to the source line. The n memory cells are operative to draw current from the source line in response to an n bit data word. A dummy memory cell circuit is operative to draw current from the source line responsive to the n bit data word such that a total current drawn by the memory cell array and the dummy memory cell circuit during a program operation is given by n*a current drawn by one of the n memory cells.

Integrated circuit memory devices and methods of programming the same in which the current drawn during a programming operation is independent of the data to be programmed

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Yongin-si, South Korea

Soung-Hoon Sim