Sharp Kabushiki Kaisha Corporation

Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Sanyo Electric Co., Ltd.

Sharp Corporation

Japan Radio Co., Ltd.

Souichi Miyata

Tsuyoshi Muramatsu

Satoshi Matsumoto

Kenji Shima

Shinichi Yoshida

Shinji Komori

Hiroaki Terada

Hajime Asano

Masahisa Shimizu

Hiroki Miura

Katsuhiko Asada

Hiroaki Nishikawa

Daisuke Azuma

Masaharu Tomita

Tatsuyuki Kuwabara

Kiyotaka Nagamura

Takao Nakamura

Koji Komatsu

Shin'ichi Yoshida

Toshiya Okamoto

Ryuji Miyama

Futoshi Miyamae

Niroaki Nishikawa

Manabu Yumoto

Tetsuo Yamasaki

Takeshi Fukuhara

Shingo Nomura

Kouichi Hatakekyama

Katushiko Asada

Toshiaki Terasaka

A data flow information processing apparatus includes one or a plurality of data driven type processors for processing data packets based on a data flow program, one or a plurality of memories accessed by these processors, and a router receiving data packets processed by these data processors for selecting a path for selectively applying the data packet to any of the one or the plurality of memories. More preferably, a first router includes an address calculating unit for calculating the address based on the content of the data packet, and a branching unit for branching the path of the data packet based on the calculated address. The data packet includes a generation number allotted in accordance with the order of input time and data. The address calculating unit includes a unit for calculating a modified address by modifying the generation number based on the data. The address modifying unit may include a circuit for modifying the generation number with a prescribed global offset, and a circuit for calculating a locally offset address by further modifying the generation number with the data included in the applied data packet.

Data driven type information processing apparatus including plural data

A data transfer control unit for controlling data transfer between a main processing part executing information processing and a memory part accessed by the main processing part has a bit width control part for controlling the bit width of the transferred data so that a first bit width of a port for data input/output on the main processing part side is matched with a second bit width, which is narrower than the first bit width, of a port for data input/output on the memory part side. This bit width control part has a function of converting the bit width of the data to the second bit width in case of data transfer from the main processing part to the memory part and a function of converting the same to the first bit width in case of data transfer from the memory part to the main processing part. Thus, the capacity of the memory part can be reduced by adjusting the bit width of the data transferred between the main processing part and the memory part.

Data transfer control unit for reducing memory requirements in an

A data driven type information processor includes a data driven type information processing unit, and a download unit. The information processing unit includes a program storing unit and an input/output control unit of a data packet for storing information stored in a data packet including a load instruction into the program storing unit and for carrying out a data driven type process on data packets including other instructions according to information stored in the program storing unit. The download unit downloads program data to the information processing unit by applying a data packet including the load instruction and program data to be stored in the program storing unit. The download unit includes a memory for storing program data, a readout circuit for reading out a set of program data stored in the memory, and a packet generation circuit for generating a data packet including the load instruction and readout program data to provide the same to the input/output control unit of the information processing unit. The memory may store a plurality of sets of program data.

Stand-alone data driven type information processor

The present invention relates to a data flow process changing system for relieving the process executed in a data flow processor and further for changing the constant in the process of the data flow processor. The data flow process changing system includes a counter section for counting the number of input data, a destination number selecting section for selecting a destination number corresponding to the counted number of input data and a tagging section for forming a packet. When a destination number corresponding to the counted number of input data is selected in the data flow process changing system, the program executed in the data flow processor can be changed. In the data flow process changing system, a constant change data generating section is responsive to a constant change request to generate a constant change data, and a destination number selecting and tagging section forms a packet addressing the destination number of a constant change program. When the packet is provided to the data flow processor, the constant change program updates the constant of the constant table store, in which the constant used in the main program has been stored, to a predetermined constant.

Data flow processor and data flow process changing system

Data driven type information processing apparatus

A data driven type information processor includes a control unit having a function of storing a data flow program and accessing it, and a function of producing an operand data pair, the control unit further including one memory shared by both functions. When a program is executed, program data per 1 accessing to the memory and operand data related to the program data are read out simultaneously and applied to an operation unit. Accordingly, a program memory and a memory for queuing operand data, which, were separately provided in a conventional technique, are combined into a single mechanism. Thereby, the number of stages of processing in program execution in the information processor is reduced and increase in program execution speed is permitted.

Data driven type information processor including a combined program

In a data-flow type computer using paired data, the improvement of a data transmission apparatus wherein the difference in the number of data pieces written in a memory and the number of data pieces read out from the memory is determined. If this difference exceeds a predetermined number, a transmission inhibiting signal is generated from an inhibiting signal generating portion to be applied to a merging portion, wherein the merging portion temporarily inhibits the merging of data from an external data memory or external information processing unit and then allows for the merging of data when the difference becomes less than the predetermined number.

Data driven computer producing inhibit signal for inhibiting merging

A memory interface device capable of memory accessing suitable for video image signal processing and memory accessing designating an arbitrary address. The interface includes an input scrambler for rewriting the generation number of an input data packet utilizing first data and/or second data when the instruction code of the input data packet is a table conversion instruction, and otherwise outputting the input data packet as it is, and a memory accessing circuit accessing an image memory using the generation number of the applied input data packet as an address and outputting the result of accessing. The device produces and outputs an output data packet from the result of accessing output from the memory accessing circuit and the input data packet.

Memory interface

A data processing system includes a data driven processor for carrying out a plurality of different information processing in parallel using respective plurality of provided data packets, a router, and a plurality of von Neumann processors. When a von Neumann processor provides program data packets to the data driven processor via the router to carry out program loading in the data driven processor, another von Neumann processor provides to the data driven processor a data packet storing dumping information via the router. The data driven processor dumps and provides a loaded program data according to the dumping instruction of the provided packet. Therefore, a plurality of von Neumann processors can be connected on-line to at least one data driven processor to carry out in parallel a plurality of different types of data transfer between the data driven processor and each von Neumann processor. These transfers include: (1) dumping a loaded program data packet to a von Neumann processor during loading of other program data packets for on-line verification of proper loading; and (2) outputting an operation result, of an operation process performed by the data driven processor, to the von Neumann processor for verification of proper operation processing during the continued operation processing of the data driven processor.

Debugging system for the loading and execution of data flow programs

A system having multiple data flow processors is provided which can independently test the operation of each individual data flow processor so that any failure found in the test will easily be located. A host computer is selectively connected to one of a plurality of data flow processors through a switching unit. The switching unit can select one of the data flow processors which can independently be tested.

System having multiple data flow processors and switching unit for

A data driven type information processing apparatus includes an information processing unit for carrying out an operation process according to a data flow program based on a data packet with a tag attached thereto, and a tag attaching unit provided in an input stage of the information processing unit. The tag attaching unit attaches a prescribed tag to data without a tag, which is applied externally or from another information processing apparatus connected on-line to generate a tagged data packet, and applies the tagged packet to the information processing unit. An information processing apparatus which is connected on-line to the present information processing apparatus and mutually exchanges the processed data mutually is not limited to either von Neumann type or non Neumann type (data driven type). Accordingly, the data driven type information processing apparatus of the present invention can be used together with various types of information processing apparatus, and a system capable of processing both tagged and untagged data can be constructed.

Data driven type information processing apparatus capable of processing

So-called template matching processing is function-distributed into a pre-detecting portion and a template matching portion, processing in the respective portions being achieved by a hardware circuit. In the pre-detecting portion, the relationship between data which simultaneously exist in the determined comparing sections on data transmission paths, and matching processing is performed in advance with respect to data to be matched. The template matching portion includes an addressing type general-purpose memory and performs main processing of template matching based on the result of the comparison and determination in the pre-detecting portion.

Data processor for detecting identical data coexisting in a plurality of

A data transmission apparatus includes one input-side transmission path and a plurality of output-side transmission paths. The input-side transmission path includes a plurality of handshaking-type data transmission paths provided in series. Each of the output-side transmission paths includes a plurality of handshaking-type data transmission paths provided in series. Data to be transmitted includes an identifier for designation any or all of the plurality of output-side transmission paths. A comparison and determination logic portion determines whether the identifier included in the data designates any of the plurality of output-side transmission paths or all of them. A control portion sends the data supplied from the input-side transmission path to any or all of the plurality of output-side transmission paths, in response to a signal outputted from the comparison and determination logic portion.

Data transmission apparatus

A refresh control circuit includes a refresh request generating circuit, a multiplexer, a memory access control circuit and an elimination control circuit. The refresh request generating circuit periodically outputs a transfer pulse and a refresh packet for refreshing. The merging control circuit receives a transfer pulse for normal access and a transfer pulse for refreshing. The merging control circuit, when the transfer pulse for refreshing and the transfer pulse for normal access contend with each other, applies first the transfer pulse to the memory access control circuit, makes the other stand by and generates an identification signal for identifying normal access and refreshing. The multiplexer receives a refresh packet and a data packet and applies one of the packets to the memory access control circuit in response to the identification signal. The memory access control circuit selectively controls a normal access operation based on the data packet or a refresh operation based on the refresh packet in response to the identification signal to output a transfer pulse. When an identification signal indicates a refresh operation, the elimination control circuit eliminates a transfer pulse output from the memory access control circuit.

Refresh control circuit for memory

An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

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Nara, Japan

Souichi Miyata