Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics (crolles 2) Sas

Sotirios Athanasiou

Philippe Galy

Laurent Grenouillet

Sylvain Engels

Julien Le Coz

A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

Transistor structure

An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

Device for protection against electrostatic discharges with a distributed trigger circuit

A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Substrate contact land for an MOS transistor in an SOI substrate, in particular an FDSOI substrate

An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate

The invention relates to an integrated circuit (), comprising:

Integrated circuit cointegrating a FET transistor and a RRAM memory point

An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.

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Grenoble, France

Sotirios Athanasiou