Renesas Electronics Corporation

Synaptics Corporation

Sosuke Tsuji

Masaru Iizuka

Shinobu Nohtomi

Hirofumi Sonoyama

Iori Shiraishi

Hikaru Shibahara

Yuri Naka

Hiroto Kinno

Orimitsu Serizawa

A display system includes a sender and a display driver. The sender is configured to provide first extended pixel data for a first pixel. The first extended pixel data includes first pixel data and a first process select bit. The display driver is configured to receive the first extended pixel data. The display driver is further configured to apply, based on the first process select bit, one or more first processes to the first pixel data, and drive a display panel based on the first extended pixel data.

Devices and methods for controlling pixel data processing

A display driver comprises a decoder, a first source amplifier and a logic circuitry. The decoder is configured to output a grayscale voltage corresponding to an image data. The first source amplifier is configured to output a first source output voltage corresponding to the grayscale voltage to a first external output terminal. The logic circuitry is configured to generate fault detection data for fault detection of a test object connected to the first external output terminal. The fault detection data is based on a comparison output signal generated based on a comparison between a reference voltage and a voltage on the first external output terminal. The comparison is performed by the first source amplifier.

Device and method for testing interconnection of display module

The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.

Semiconductor integrated circuit device for display controller

The present invention provides a display control semiconductor integrated circuit having therein a RAM, capable of repairing a defective bit included in the RAM and improving the yield without significantly increasing the occupation area. A liquid crystal controller/driver in which a RAM for storing display data is provided in a chip and the storage capacity of the built-in RAM is determined according to the size of a display screen of a liquid crystal panel to be driven, includes a fuse circuit for setting a defect address, and a comparing circuit for comparing the defect address set in the fuse circuit with an input address. The liquid crystal controller/driver also has a redundant circuit, when the addresses match each other, for replacing the input address with an address that instructs the spare memory area and supplying the address to an address decoder.

Display control semiconductor integrated circuit

The present invention is directed to repair a defective bit included in a memory in a semiconductor integrated circuit device for a display controller. The semiconductor integrated circuit device has a display memory capable of storing display data in a storage area, and a repair circuit capable of repairing a defect by replacing an area including a defect in the display memory with a spare storage area provided on the outside of a regular storage area for storing the display data. The device further includes a selector circuit provided on a transmission path of output data from the display memory and selectively replacing output data from the regular storage area with output data from the spare storage area in accordance with a control signal from the repair circuit. By selectively replacing the output data from the regular storage area with output data from the spare storage area in accordance with a control signal from the repair circuit, a defective bit is repaired.

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Tokyo, Japan

Sosuke Tsuji