Renesas Electronics Corporation

Renesas Technology Corp.

Renesas Electronics Coporation

Soshi Kuroda

Masatoshi Yasunaga

Kenya Hironaga

Hironori Matsushima

Akira Yamazaki

Tatsuya Hirai

Tatsuya Kobayashi

Yosuke Imazeki

Koji Bando

Takanori Aoki

Hideyuki Arakawa

Naoya Yasuda

A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface, a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate, and a plurality of wires electrically connected with the plurality of terminals, respectively.

Semiconductor device

A BGAincludes a wiring substrate, a semiconductor chipfixed on the wiring substrate, a sealing bodythat seals the semiconductor chip, and a plurality of solder ballsprovided on a lower surface of the wiring substrate. A degree of flatness of an upper surfaceof a first wiring layerof the wiring substrateof the BGAis lower than a degree of flatness of a lower surface, and a first patternprovided in a second wiring layeris arranged at a position overlapping a first patternprovided in the first wiring layer. Also, an area of the first patternprovided in the first wiring layeris larger than an area of a plurality of (for example, two) second patternsprovided in the second wiring layerin a plan view, and a first opening portionthrough which a part of a second insulating layeris exposed is formed in the first patternprovided in the second wiring layer

Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Method of manufacturing semiconductor device

To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.

Semiconductor device and method of manufacturing same

To enhance the reliability of a semiconductor device. The semiconductor device includes a wiring substrate having a plurality of bonding fingers (terminal) formed on a chip-mounting surface, a semiconductor chip mounted on the wiring substrate, a plurality of wires having a ball part and a stitch part respectively. The bonding fingers have a first bonding finger to which the stitch part of the first wire is coupled respectively, and the second bonding finger to which a ball part of the second wire is coupled. In addition, in plan view, the second bonding finger is arranged at a position different from the arrangement of a plurality of first bonding fingers, and the width of the second bonding finger is larger than the width of the first bonding finger.

Semiconductor device and method of manufacturing the same

To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Semiconductor device with copper wire having different width portions

To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100&#xb0; C. to 150&#xb0; C. for dehumidification, a heat treatment (second heat treatment) at 160&#xb0; C. to 230&#xb0; C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Manufacturing method of semiconductor device

Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100&#xb0; C. to 150&#xb0; C. for dehumidification, a heat treatment (second heat treatment) at 160&#xb0; C. to 230&#xb0; C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

A semiconductor device in which memory chips are stacked on the surface of a wiring substrate has a microcomputer chip and an interposer chip arranged on the surface of the memory chip. The pads of the microcomputer chip and the pads of the interposer chip are arranged almost circularly and are connected by bonding wires.

Growing community of inventors

Kanagawa, Japan

Soshi Kuroda