Power Integrations, Inc.

Catalyst Semiconductor, Inc.

Semiconductor Components Industries, LLC

Tripath Technology, Inc.

Sorin Stefan Georgescu

Kuo-Chang Robert Yang

Hartley Fred Horwitz

George Smarandoiu

Kamal Raj Varadarajan

A Peter Cosmin

Ilie Marian I Poenaru

Anthony Gerard Russell

Chris B Bartholomeusz

Alexei Ankoudinov

Sabin A Eftimie

Adam Peter Cosmin

Vijay Parthasarathy

Robert J Mayell

Roger Colbeck

Alexey Kudymov

Radu H Iacob

Carl K Sawtell

Steven Greig Porter

Adrian Macarie Tache

Lin Zhu

Yueming Wang

Jiankang Bu

Robert W Busse

Alina I Negut

Radu Vanco

Paul Walter DeMone

Peter Cosmin

Radu A Sporea

Kelly Marcum

Toni M Wojslaw, Legal Representative

Wayne Byran Grabowski

Andrei Mihnea

Kelly E Marcum

Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region.

Capacitance networks for enhancing high voltage operation of a high electron mobility transistor and method therein

Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device are presented herein. Polysilicon guard rings are disposed above the power device drift region and electrically coupled to power device regions (e.g., device diffusions) so as to spread electric fields associated with an operating voltage. Additionally, PN junctions (i.e., p-type and n-type junctions) are formed within the polysilicon guard rings to operate in reverse bias with a low leakage current between the power device regions (e.g., device diffusions). Low leakage current may advantageously enhance the electric field spreading without deleteriously affecting existing (i.e., normal) power device performance; and enhanced electric field spreading may in turn reduce breakdown-voltage drift.

Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device

A controller includes first and second half bridge sense circuits coupled to a half bridge node. The half bridge node is coupled between a high side switch and a low side switch coupled to an input. A rising slew detection circuit is coupled to the first half bridge sense circuit to output a first slew detection signal in response to a rising slew event at the half bridge node. A falling slew detection circuit is coupled to the second half bridge sense circuit to output a second slew detection signal in response to a falling slew event at the half bridge node. A control circuit coupled to output a high side drive signal to the high side switch and a low side drive signal to the low side switch in response to the first slew detection signal, the second slew detection signal, and a feedback signal.

Deadtime adjustment for a power converter

Silicon carbide (SiC) junction field effect transistors (JFETs) are presented herein. A deep implant (e.g., a deep p-type implant) forms a JFET gate (). MET gate and MET source () may be implemented with heavily doped n-type (N+) and heavily doped p-type (P+) implants, respectively. Termination regions may be implemented by using equipotential rings formed by deep implants (e.g., deep p-type implants).

Silicon carbide junction field effect transistors

A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.

Process and structure for a superjunction device

A switch having a drain, a source, and a control. The switch comprising a depletion-mode transistor including a first, a second, and a control terminal and an enhancement-mode transistor including a first, a second, and a control terminal. The first terminal of the depletion-mode transistor is the drain of the switch and the control of the depletion-mode transistor is coupled to the source of the switch. The control of the enhancement-mode transistor is coupled to the control of the switch, the second terminal of the enhancement-mode transistor is the source of the switch. The switch comprises a clamp circuit to clamp a voltage of the first terminal of the enhancement-mode transistor to a threshold, the clamp circuit comprises a resistor and a pn-junction device coupled between the first and second terminals of the enhancement-mode transistor and between the second terminal and the control of the depletion-mode transistor.

Clamp for a hybrid switch

A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of dielectric regions disposed in the semiconductor layer. The dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Each dielectric region has a rounded-square cross-section in a horizontal plane perpendicular to the vertical direction. Adjacent ones of the dielectric regions are laterally separated by a narrow region of the semiconductor layer. Each dielectric region has a cylindrical field plate member centrally disposed therein. The cylindrical field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrical field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Vertical transistor device structure with cylindrically-shaped field plates

A switch having a first terminal, a second terminal and a control terminal. The switch includes a normally-on device with a first terminal, a second terminal, and a control terminal. The first terminal of the normally-on device is the first terminal of the switch. The control terminal of the normally-on device is coupled to the second terminal of the switch. A normally-off device includes a first terminal, a second terminal, and a control terminal. The control terminal of the normally-off device is coupled to the control terminal of the switch. The second terminal of the normally off-device is the second terminal of the switch. The first terminal of the normally-off device is coupled to the second terminal of the normally-on device. A clamp circuit is coupled across the normally-off device. The clamp circuit is coupled to clamp a voltage of the first terminal of the normally-off device to a threshold.

A cascode switch circuit includes a normally-on device cascode coupled to a normally-off device between first and second terminals of the cascode switch circuit. A leakage clamp circuit is coupled between first and second terminals of the normally-off device. The leakage clamp circuit is coupled to clamp a voltage at an intermediate terminal between the normally-on device and the normally-off device at a threshold voltage level. The leakage clamp circuit is further coupled to clamp a voltage between the second terminal of the normally-on device and the control terminal of the normally-on device at the threshold voltage level to keep the normally-on device off when the normally-on device and the normally-off device are off.

A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar.

High voltage vertical semiconductor device with multiple pillars in a racetrack arrangement

A cascode switch circuit includes a normally-on device cascode coupled to a normally-of device between first and second terminals of the cascode switch circuit. A leakage clamp circuit is coupled between first and second terminals of the normally-off device. The leakage clamp circuit is coupled to clamp a voltage at an intermediate terminal between the normally-on device and the normally-off device at a threshold voltage level. The leakage clamp circuit is further coupled to clamp a voltage between the second terminal of the normally-on device and the control terminal of the normally-on device at the threshold voltage level to keep the normally-on device off when the normally-on device and the normally-off device are off.

A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of cylindrically-shaped dielectric regions disposed in the semiconductor layer. The cylindrically-shaped dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the semiconductor layer having a first width. Each dielectric region has a cylindrically-shaped, conductive field plate member centrally disposed therein. The cylindrically-shaped, conductive field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrically-shaped, conductive field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Vertical transistor device structure with cylindrically-shaped regions

A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.

Scalable electrically erasable and programmable memory

A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.

Growing community of inventors

San Jose, CA, United States of America

Sorin Stefan Georgescu