Sun Microsystems, Inc.

Intel Corporation

Hewlett-packard Company

Institute for the Development of Emerging Architectures, L.l.c.

Hewlett-packard Development Company, L.p.

National Semiconductor Corporation

Oracle America, Inc.

Sorin Iacobovici

Rabin Sugumar

Dean A Mulla

Chandra M R Thimmannagari

Robert David Nuckolls

William R Bryg

Sreejit Chakravarty

Alberto J Munoz

Amy L Santoni

Michael Neve De Mevergnies

Neel Piyush Shah

Ramasubramanian Rajamani

Oscar Mendoza

Bryan J Gran

Joseph H Hassoun

Chandra Thimmanagari

Kirk S Yap

Kenneth Kay Smith

Thomas D Fletcher

Wei Wu

Yuan C Chou

Nhon Toai Quach

Paul N Loewenstein

Brian J Hickmann

Sudarshan Kadambi

David J Greenhill

Daniel Lawrence Leibholz

Roger Espasa

James O Hays

Guillem Sole

Moenes Zaher Iskarous

Paul M Stillwell, Jr

John Cruz Mejia

Ronald J Melanson

Valentin Anders

Loren P Staley

Ran Talmudi

Victor Melamed

John W C Fu

Motti Beck

A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

In-field system testing

A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.

In-field system test security

Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.

Consecutive bit error detection and correction

An error detection unit including one or more register files that store at least one operand and at least one operand residue, an operand multiplexor operable to receive the operand, a residue multiplexor operable to receive the operand residue, a source operand residue generator operable to generate at least one generated residue from the operand, a first comparator that compares the operand residue to the generated residue, the result of the first comparator being sent to a reorder buffer, an execution unit that supplies the operand to a residue calculator and a result residue generator, wherein the residue calculator operable to determine an expected residue and the result residue generator operable to generate a result residue, and a second comparator that compares the expected residue with the result residue, the result of the second comparator being sent to the reorder buffer.

Residue based error detection for integer and floating point execution units

Methods and apparatus to provide core sparing on multi-core platforms are described. In an embodiment, stored core state information of a target core (e.g., a core that has detected a fault condition (e.g., within its circuitry) or a request to offload operations from the target core (e.g., to enable run-time diagnostics without interfering with system software)) may be read by a spare core which is to operationally replace the target core. Other embodiments are also described.

Core sparing on multi-core platforms

A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectural state is saved to memory in response to a save state triggering event, which may include a hardware event or a software event. Once saved, the state is potentially transferred to another processing element, such as a second core. As a result, hardware, software, or combination thereof may transfer architectural states between multiple processing elements, such as threads or cores, of a processor utilizing hardware support.

Saving and restoring architectural state for processor cores

An end-to-end residue-based protection scheme protects multiple units/blocks of a floating point execution pipeline without the complexity and cost of having multiple protection schemes for the execution pipeline. Protecting an execution pipeline that supports floating point operations includes factoring in component operations, such as normalization and rounding, into a residue generated for a result. In addition, residues of operands are distilled to extract their corresponding mantissa residues, thus allowing the floating point operations (e.g., multiplication, addition, etc.) to be applied to the mantissa residues.

End-to-end residue-based protection of an execution pipeline that supports floating point operations

A processor that protects an execution pipeline includes a residue-based error detection infrastructure including a first logic for computing a first residue of a result of an executed instruction instance, and a second logic for computing a second residue of the result. The second logic applies arithmetic operations of the executed instruction instance to residues of operands of the instruction instance. The execution pipeline includes registers and one or more arithmetic execution units. A method of protecting an execution pipeline includes performing one or more operations of an instruction instance on residues of operands of the instruction instance, computing a first residue of a result of the operations on the operand residues, computing a second residue from a result of executing the instruction instance, and checking the first residue against the second residue to determine whether errors were introduced while the instruction instance was resident in the execution pipeline.

End-to-end residue based protection of an execution pipeline

Errors in a shift result can be detected with a residue-based mechanism, instead of with duplication of an entire shifter. The commutative property of residue computation over a bit string allows the residue of a value to be independent of the actual bit positions when the divisor is a Merrill number. Without a duplicated shifter, an operand that is the subject of a shift operation is formatted to become a multiple of k, where divisor=2&#x2212;1, and the divisor is used for computation of residues. The shift operation is translated to a single position shift or a zero position shift. The translated shift is applied to the formatted operand to generate a shift check value. Despite different values, the residues of the shift result and the shift check value will be the same as long as bit groups are consistent between the two. An error(s) is detected by comparing the residue of the shift check value with the residue of the shift result.

Residue-based error detection for a shift operation

A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also includes a thread number field to help support multi-threaded processor cores. The tag field stores a tag from an address associated with a cache miss. The index table includes fields for storing information characterizing a state machine. The fields include a learning bit. The multi-stride prefetcher prefetches data into a cache for a plurality of streams of cache misses, each stream having a plurality of strides.

Multi-stride prefetcher with a recurring prefetch table

A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

Versatile register file design for a multi-threaded processor utilizing different modes and register windows

The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as 'evil twins.' If there is a register dependency between a greater width producer instruction and a lesser width consumer instruction, a greater width source register is substituted for the source register specified by the lesser width producer. If there is a register dependency between a lesser width producer instruction and a greater width producer instruction, the greater width consumer instruction is replaced by multiple helper instructions. One or more of the helper instructions merge lesser width registers aliased onto the source registers specified by the greater width consumer instruction, into temporary registers. Another helper instruction executes the greater width consumer instruction using the temporary registers instead of the original source registers.

Handling register dependencies between instructions specifying different width registers

Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main memory. By keeping track of the source of cache lines in the on-chip cache memory and by designing the replacement algorithm of the on-chip cache memory such that only one line in a given set maps into an off-cache memory cache line, the frequency of off-chip cache memory accesses may be greatly reduced, thereby improving performance and efficiency.

Techniques for reducing off-chip cache memory accesses

The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.

Vector technique for addressing helper instruction groups associated with complex instructions

A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream

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San Jose, CA, United States of America

Sorin Iacobovici